Cancer treatment: an overview of pulsed electric field utilization and generation

Patients diagnosed with cancer receive different types of treatments based on the type and the level of the tumour. An emerging treatment that differs from well-developed systematic therapies (i.e., Chemotherapy, Radiotherapy, and Immunotherapy) is Tumour Treating Field (TTF) treatment. Tumour behaviour under TTF treatment varies based on the electric field intensity; the process of exposing the tumour cells to an electric field is called electroporation. From the electrical perspective, the most efficient method for electroporation is to use a voltage pulse generator. Several pulse generator topologies have been introduced to overcome existing limitations, mitigate the drawbacks of classical generators, and provide more controllable, flexible, and portable solid-state voltage pulse generators. This paper provides a review of cancer treatment using TTF and highlights the key specifications required for efficient treatment. Additionally, potential voltage pulse generators are reviewed and compared in terms of their treatment efficacy and efficient use of electrical power

Efficient Superconductor Arithmetic Logic Unit for Ultra-Fast Computing

We present a 4-bit Arithmetic Logic Unit (ALU) utilizing superconductor technology. The ALU serves as the central processing unit of a processor, performing crucial arithmetic and logical operations. We have adopted a bit-parallel architecture to ensure an efficient and streamlined design with minimal fanin/fanout and optimal latency. In terms of fabrication, the ALU has been fabricated using a standard commercial process. It operates at an impressive clock frequency exceeding 30 GHz while consuming a mere 4.75 mW of power, including applied reverse current, encompassing static and dynamic components. The ALU contains over 9000 Josephson junctions, with approximately 7000 JJs dedicated to wiring, delay lines, and path balancing, and it has over 18% bias margin. Designed as a co-processor, this arithmetic logic unit will work with external CMOS memory and processors via interface circuits. Thorough testing and validation of the ALU's functionality have been conducted with digital and analog simulations, and all the components were fabricated and measured within a 4K pulse-tube cryocooler. Experimental verification has confirmed the successful operation of both the arithmetic and logic units. These results have been analyzed and are presented alongside the experimental data to provide comprehensive insights into the ALU's behavior and capabilities.Comment: 11 pages, 10 figures and 37 reference

Low-power emerging memristive designs towards secure hardware systems for applications in internet of things

Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and in-memory computing (IMC), but there is a rising interest in using memristive technologies for security applications in the era of internet of things (IoT). In this review article, for achieving secure hardware systems in IoT, low-power design techniques based on emerging memristive technology for hardware security primitives/systems are presented. By reviewing the state-of-the-art in three highlighted memristive application areas, i.e. memristive non-volatile memory, memristive reconfigurable logic computing and memristive artificial intelligent computing, their application-level impacts on the novel implementations of secret key generation, crypto functions and machine learning attacks are explored, respectively. For the low-power security applications in IoT, it is essential to understand how to best realize cryptographic circuitry using memristive circuitries, and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security. This review article aims to help researchers to explore security solutions, to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs

The CARMA correlator

The Combined Array for Research in Millimeter-wave Astronomy (CARMA) requires a flexible correlator to process the data from up to 23 telescopes and up to 8GHz of receiver bandwidth. The Caltech Owens Valley Broadband Reconfigurable Array (COBRA) correlator, developed for use at the Owens Valley millimeter-wave array and being used by the Sunyaev-Zeldovich Array (SZA), will be adapted for use by CARMA. The COBRA correlator system, a hybrid analog-digital design, consisting of downconverters, digitizers and correlators will be presented in this paper. The downconverters receive an input IF of 1-9GHz and produce a selectable output bandwidth of 62.5MHz, 125MHz, 250MHz, or 500MHz. The downconverter output is digitized at 1Gsample/s to 2-bits per sample. The digitized data is optionally digitally filtered to produce bands narrower than 62.5MHz (down to 2MHz). The digital correlator system is a lag- or XF-based system implemented using Field-Programmable Gate Arrays (FPGAs). The digital system implements delay lines, calculates the autocorrelations for each antenna, and the cross-correlations for each baseline. The number of lags, and hence spectral channels, produced by the system is a function of the input bandwidth; with the 500MHz band having the coarsest resolution, and the narrowest bandwidths having the finest resolution