An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis

Accepted versio

Severity parameter and global importance factor of non-newtonian models in 3D reconstructed human left coronary artery

This paper was presented at the 3rd Micro and Nano Flows Conference (MNF2011), which was held at the Makedonia Palace Hotel, Thessaloniki in Greece. The conference was organised by Brunel University and supported by the Italian Union of Thermofluiddynamics, Aristotle University of Thessaloniki, University of Thessaly, IPEM, the Process Intensification Network, the Institution of Mechanical Engineers, the Heat Transfer Society, HEXAG - the Heat Exchange Action Group, and the Energy Institute.The capabilities and limitations of various molecular viscosity models, when testing Left Coronary Artery (LCA) tree, were analyzed via: molecular viscosity, local and global non-Newtonian importance factors, Wall Shear Stress (WSS) and Wall Shear Stress Gradient (WSSG). Seven non-Newtonian molecular viscosity models, plus the Newtonian one, were compared. Dense grid of 620000 nodes located, mostly, at near to low WSS flow regions (endothelium regions) is needed for current LCA application. The WSS distribution yields a consistent LCA pattern for nearly all non-Newtonian models. High molecular viscosity, low WSS low WSSG values appear at proximal LCA regions at the outer walls of the major bifurcation. The global importance factor for the non-Newtonian power law model yields 76.7% (non-Newtonian flow), while for the Generalized power law model this value is 6.1% (Newtonian flow). The capabilities of the applied non-Newtonian law models appear at low strain rates. The Newtonian blood flow treatment is considered to be a good approximation at mid-and high-strain rates. In general, the non-Newtonian power law and the Generalized power law blood viscosity models are considered to approximate the molecular viscosity and WSS calculations in a more satisfactory way

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Operation of transition edge sensors in a resistance locked loop

We propose to operate a superconducting transition edge sensor (TES) using a different type of biasing, in which the resistance of the TES is kept constant by means of feedback on the bias voltage and is independent of the incoming signal power. By combining a large negative electrothermal feedback with a load independent resistance, this approach can significantly linearise the response of the detector in the large signal limit. The electrothermal feedback is enhanced in comparison with the commonly applied voltage biasing, which further increases the speed of the detector. Furthermore, in frequency domain multiplexed (FDM) readout, the sinusoidal bias voltages for each TES can be generated cryogenically with the readout SQUIDs.Comment: 4 pages, 2 figure

A committee machine gas identification system based on dynamically reconfigurable FPGA

This paper proposes a gas identification system based on the committee machine (CM) classifier, which combines various gas identification algorithms, to obtain a unified decision with improved accuracy. The CM combines five different classifiers: K nearest neighbors (KNNs), multilayer perceptron (MLP), radial basis function (RBF), Gaussian mixture model (GMM), and probabilistic principal component analysis (PPCA). Experiments on real sensors' data proved the effectiveness of our system with an improved accuracy over individual classifiers. Due to the computationally intensive nature of CM, its implementation requires significant hardware resources. In order to overcome this problem, we propose a novel time multiplexing hardware implementation using a dynamically reconfigurable field programmable gate array (FPGA) platform. The processing is divided into three stages: sampling and preprocessing, pattern recognition, and decision stage. Dynamically reconfigurable FPGA technique is used to implement the system in a sequential manner, thus using limited hardware resources of the FPGA chip. The system is successfully tested for combustible gas identification application using our in-house tin-oxide gas sensors

Threshold Study of Phase Lock Loop Systems Interim Technical Report

Threshold studies of phase lock loop systems - effect of phase comparator on overall performance and threshold phenomen

Approximate Computing Survey, Part I: Terminology and Software & Hardware Approximation Techniques

The rapid growth of demanding applications in domains applying multimedia processing and machine learning has marked a new era for edge and cloud computing. These applications involve massive data and compute-intensive tasks, and thus, typical computing paradigms in embedded systems and data centers are stressed to meet the worldwide demand for high performance. Concurrently, the landscape of the semiconductor field in the last 15 years has constituted power as a first-class design concern. As a result, the community of computing systems is forced to find alternative design approaches to facilitate high-performance and/or power-efficient computing. Among the examined solutions, Approximate Computing has attracted an ever-increasing interest, with research works applying approximations across the entire traditional computing stack, i.e., at software, hardware, and architectural levels. Over the last decade, there is a plethora of approximation techniques in software (programs, frameworks, compilers, runtimes, languages), hardware (circuits, accelerators), and architectures (processors, memories). The current article is Part I of our comprehensive survey on Approximate Computing, and it reviews its motivation, terminology and principles, as well it classifies and presents the technical details of the state-of-the-art software and hardware approximation techniques.Comment: Under Review at ACM Computing Survey

Design of Unsigned Approximate Hybrid Dividers based on Restoring Array and Logarithmic Dividers

Approximate computer arithmetic has been extensively studied due to its advantages to further reduce power consumption and increase performance at reduced accuracy. Although a number of approximate adders and multipliers have been studied, only a few approximate dividers have been proposed. A logarithmic divider (LD) has low complexity and accuracy, while an exact array divider (EXD) has a high complexity. Therefore, in this paper, an approximate hybrid divider (AXHD) is proposed. It takes advantage of both LD and EXD to achieve a tradeoff between hardware performance and accuracy. Exact restoring divider cells are used to generate the most significant bits (MSBs) of the quotient for attaining a high accuracy while the other quotient digits are generated by using a LD as an approximate scheme to improve figures of merit such as power consumption, area and delay. To further save hardware resources, a so-called eliminated approximate hybrid divider (E-AXHD) based on AXHD is also proposed. In this improved design, a reduced width divider is used to replace the EXD in AXHD. Specifically, for a 16-by-8 design, n=(n + 1) array division is used to replace the n=8 array division (n < 8). The proposed AXHD and E-AXHD are evaluated and analyzed using error and hardware metrics. The proposed designs are also compared with EXD, LD and previous approximate dividers. The results show that the proposed designs outperform previous approximate dividers by considering both energy and error. The proposed hybrid dividers are of particular interest for error tolerant applications such as image processing and machine learning