A low-complexity soft-decision decoding architecture for the binary extended Golay code

International audienceThe (24, 12, 8) extended binary Golay code is a well-known rate-1/2 short block-length linear error-correcting code with remarkable properties. This paper investigates the design of an efficient low-complexity soft-decision decoding architecture for this code. A dedicated algorithm is introduced that takes advantage of the code’s properties to simplify the decoding process. Simulation results show that the proposed algorithm achieves close to maximum-likelihood performance with low computational cost. The decoder architecture is described, and VLSI synthesis results are presented

Design and implementation of a near maximum likelihood decoder for Cortex codes

International audienceThe Cortex codes form an emerging family among the rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient Maximum Likelihood (ML) decoder for Cortex codes. It first reviews a dedicated architecture that takes advantage of the particular structure of this code to simplify the decoding. Then, we propose a technique to improve the architecture by the generation of an optimal list of binary vectors. An optimal stopping criterion is also proposed. Simulation results show that the proposed architecture achieves an excellent performance/complexity trade-off for short Cortex codes. The proposed decoder architecture has been implemented on an FPGA device for the (24,12,8) Cortex code. This implementation supports an information throughput of 225 Mb/s. At a signal-tonoise ratio Eb/No=8 dB, the Bit Error Rate equals 2 × 10^−10, which is close to the performance of the Maximum Likelihood decoder

Design and implementation of a soft-decision decoder for Cortex codes

International audienceCortex codes are a family of rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient soft-decision decoder for Cortex codes. A dedicated algorithm is introduced that takes advantage of the particular structure of the code to simplify the decoding. Simulation results show that the proposed algorithm achieves an excellent trade-off between performance and complexity for short Cortex codes. A decoder architecture for the (32,16,8) Cortex code based on the (4,2,2) Hadamard code has been successfully designed and implemented on FPGA device. To our knowledge, this is the first efficient digital implementation of a soft-decision Cortex decoder

Polynomials in Error Detection and Correction in Data Communication System

The chapter gives an overview of the various types of errors encountered in a communication system. It discusses the various error detection and error correction codes. The role of polynomials in error detection and error correction is discussed in detail with the architecture for practical implementation of the codes in a communication channel

Iterative decoding for error resilient wireless data transmission

Both turbo codes and LDPC codes form two new classes of codes that offer energy efficiencies close to theoretical limit predicted by Claude Shannon. The features of turbo codes include parallel code catenation, recursive convolutional encoders, punctured convolutional codes and an associated decoding algorithm. The features of LDPC codes include code construction, encoding algorithm, and an associated decoding algorithm. This dissertation specifically describes the process of encoding and decoding for both turbo and LDPC codes and demonstrates the performance comparison between theses two codes in terms of some performance factors. In addition, a more general discussion of iterative decoding is presented. One significant contribution of this dissertation is a study of some major performance factors that intensely contribute in the performance of both turbo codes and LDPC codes. These include Bit Error Rate, latency, code rate and computational resources. Simulation results show the performance of turbo codes and LDPC codes under different performance factors

Digital VLSI Architectures for Advanced Channel Decoders

Error-correcting codes are strongly adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probes. New and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. This work aims to focus on Polar codes, which are a recent class of channel codes with the proven ability to reduce decoding error probability arbitrarily small as the block-length is increased, provided that the code rate is less than the capacity of the channel. This property and the recursive code-construction of this algorithms attracted wide interest from the communications community. Hardware architectures with reduced complexity can efficiently implement a polar codes decoder using either successive cancellation approximation or belief propagation algorithms. The latter offers higher throughput at high signal-to-noise ratio thanks to the inherently parallel decision-making capability of such decoder type. A new analysis on belief propagation scheduling algorithms for polar codes and on interconnection structure of the decoding trellis not covered in literature is also presented. It allowed to achieve an hardware implementation that increase the maximum information throughput under belief propagation decoding while also minimizing the implementation complexity

A STUDY ON WIRELESS COMMUNICATION ERROR PERFORMANCE AND PATH LOSS PREDICTION

One channel model that characterises multipath fading effect of a wireless channel is called Flat Rayleigh Fading channel model. Given the properties of Flat Rayleigh Fading channel, an equation to find the capacity of a Flat Rayleigh fading channel with hard decision decoding is derived. The difference of power requirement to achieve the Additive White Gaussian Noise (AWGN) capacity over a Flat Rayleigh Fading channel fading is found to increase exponentially with Es /N0 . Upper and lower bounds of error performance of linear block codes over a Flat Rayleigh Fading channel are also studied. With the condition that the excess delay of a channel is known earlier, it is shown that a correlator with shorter length, according to excess delay of the channel, can be constructed for use in wireless channel response measurements. Therefore, a rule of construction of a shorter length correlator is defined, involving concatenation of parts of a Constant Amplitude Zero Auto-Correlation (CAZAC) sequence. Simulation of [136,68,24] Double Circulant Code with Dorsch List Decoding is also done in order to evaluate error performance of the channel coding scheme over one of the IEEE Wireless Metropolitan Area Network (WirelessMAN) channel models, the Stanford University Interim Channel Model No. 5 (SUI-5) channel. Performance of the channel cod- ing was severely degraded over the SUI-5 channel when it is compared to its performance over the AWGN channel. Indoor path losses within three multifloor office buildings were investigated at 433 MHz, 869 MHz and 1249 MHz. The work involved series of extensive received signal strength measurements within the buildings for all of the considered frequencies. Results have shown that indoor path loss is higher within a square footprint building than indoor path loss in a rectangular building. Parameters of Log-Distance Path Loss and Floor Attenuation Factor Path Loss models have been derived from the measurement data. In addition, a new indoor path loss prediction model was derived to cater for path loss pre- diction within multifloor buildings with indoor atriums. The model performs with better prediction accuracy when compared with Log-Distance Path Loss and Floor Attenuation Factor Path Loss models.Ministry of Higher Education of Malaysia, Universiti Teknologi Malaysi

On Multiple Decoding Attempts for Reed-Solomon Codes: A Rate-Distortion Approach

One popular approach to soft-decision decoding of Reed-Solomon (RS) codes is based on using multiple trials of a simple RS decoding algorithm in combination with erasing or flipping a set of symbols or bits in each trial. This paper presents a framework based on rate-distortion (RD) theory to analyze these multiple-decoding algorithms. By defining an appropriate distortion measure between an error pattern and an erasure pattern, the successful decoding condition, for a single errors-and-erasures decoding trial, becomes equivalent to distortion being less than a fixed threshold. Finding the best set of erasure patterns also turns into a covering problem which can be solved asymptotically by rate-distortion theory. Thus, the proposed approach can be used to understand the asymptotic performance-versus-complexity trade-off of multiple errors-and-erasures decoding of RS codes. This initial result is also extended a few directions. The rate-distortion exponent (RDE) is computed to give more precise results for moderate blocklengths. Multiple trials of algebraic soft-decision (ASD) decoding are analyzed using this framework. Analytical and numerical computations of the RD and RDE functions are also presented. Finally, simulation results show that sets of erasure patterns designed using the proposed methods outperform other algorithms with the same number of decoding trials.Comment: to appear in the IEEE Transactions on Information Theory (Special Issue on Facets of Coding Theory: from Algorithms to Networks