Design of a Class-AB Amplifier for a 1.5 Bit MDAC of a 12 Bit 100MSPS Pipeline ADC

The basic building block of a pipeline analog-to-digital converter (ADC) is the multiplying digital-to-analog converter (MDAC). The performance of the MDAC significantly depends on the performance of the operational amplifier and calibration techniques. To reduce the complexity of calibration, the operational amplifier needs to have high-linearity, high bandwidth and moderate gain. In this work, the Op-amp specifications were derived from the pipeline ADC requirements. A novel class-AB bias scheme with feed-forward compensation, which provides high linearity and bandwidth consuming low power is proposed. The advantages of the new topology over Monticelli bias scheme and Miller’s compensated amplifiers is explained. The amplifier is implemented in IBM 130nm technology and the MDAC design is used as a test bench to characterize the Op-amp performance. The proposed architecture performance is compared with class A and class-AB output stage amplifiers with Miller’s compensation reported in literature. The proposed class-AB amplifier with feed forward compensation provides an open loop gain of 47dB, unit gain bandwidth of 1040 MHz and IM3 of 75dB consuming 3.88mA current. The amplifier provides the required linearity and bandwidth at much lower power consumption than the amplifiers using conventional class-AB bias schemes

Projeto de uma nova arquitetura para conversores de sinais analógicos para digitais

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Elétrica, Programa de Pós-graduação em Engenharia Elétrica, 2015.The objective of this work is the development and design of a new architecture for the ADC Difference Module Converter (CMD). The proposed converter CMD is characterized by being asynchronous without oversample and with only one cycle for conversion. Its topology doesn´t presents feedback, does not use capacitors nor resistors, does not use Sample-and-hold circuit (S / H) and has only one reference to conversion. The project was developed in current mode, which not use Op-amp in the circuit for the conversion. And the project also has a digital circuit with only one XNOR gate per bit. We can highlight that each bit is simultaneously converted by a continuous process and that your conversion code is stable, i.e., varying only one bit between adjacent digital words.O objetivo deste trabalho é o desenvolvimento e projeto de uma nova arquitetura para ADC o Conversor do Módulo da Diferença (CMD). O Conversor CMD proposto se caracteriza por ser assíncrono, sem oversample e com apenas um ciclo para conversão. Sua topologia não apresenta realimentação, não utiliza capacitores nem resistores, não utiliza circuito de Sample-and-Hold (S/H) e possui apenas uma referência para conversão. O projeto foi desenvolvido em modo corrente, o que permitiu não utilizar Amp-Op no circuito destinado à conversão. E o projeto também possui um circuito digital com apenas uma porta XNOR por bit. Podemos destacar que os bit são convertidos simultaneamente por um processo contínuo e que seu código de conversão é estável por variar apenas um bit entre palavras digitais adjacentes

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer EngineeringThe work presented in this thesis addresses the task of circuit optimization, helping the designer facing the high performance and high efficiency circuits demands of the market and technology evolution. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier. The main advantage of this new time-domain methodology is that, when a given settling-error is reached within the desired settling-time, it is automatically guaranteed that the amplifier has enough open-loop gain, AOL, output-swing (OS), slew-rate (SR), closed loop bandwidth and closed loop stability. Thus, this simplification of the circuit‟s evaluation helps the optimization process to converge faster. The method used to calculate the step response expression of the circuit is based on the inverse Laplace transform applied to the transfer function, symbolically, multiplied by 1/s (which represents the unity input step). Furthermore, may be applied to transfer functions of circuits with unlimited number of zeros/poles, without approximation in order to keep accuracy. Thus, complex circuit, with several design/optimization degrees of freedom can also be considered. The expression of the step response, from the proposed methodology, is based on the DC bias operating point of the devices of the circuit. For this, complex and accurate device models (e.g. BSIM3v3) are integrated. During the optimization process, the time-domain evaluation of the amplifier is used by the genetic algorithm, in the classification of the genetic individuals. The time-domain evaluator is integrated into the developed optimization platform, as independent library, coded using C programming language. The genetic algorithms have demonstrated to be a good approach for optimization since they are flexible and independent from the optimization-objective. Different levels of abstraction can be optimized either system level or circuit level. Optimization of any new block is basically carried-out by simply providing additional configuration files, e.g. chromosome format, in text format; and the circuit library where the fitness value of each individual of the genetic algorithm is computed. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. The communication by remote processing nodes is based on Message Passing interface (MPI). It is demonstrated that the distributed processing reduced the optimization run-time by more than one order of magnitude. Platform assessment is carried by several examples of two-stage amplifiers, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out and fabricated as a stand-alone circuit and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.Portuguese Foundation for the Science and Technology (FCT