Design and Implementation of Low Power SRAM Using Highly Effective Lever Shifters

The explosive growth of battery-operated devices has made low-power design a priority in recent years. In high-performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for SRAM memory devices since they are a dominant source of standby power consumption in low-power application processors. The on-die SRAM power consumption is particularly important for increasingly pervasive mobile and handheld applications where battery life is a key design and technology attribute. In the SRAM-memory design, SRAM cells also comprise the most significant portion of the total chip. Moreover, the increasing number of transistors in the SRAM memories and the MOSs\u27 increasing leakage current in the scaled technologies have turned the SRAM unit into a power-hungry block for both dynamic and static viewpoints. Although the scaling of the supply voltage enables low-power consumption, the SRAM cells\u27 data stability becomes a major concern. Thus, the reduction of SRAM leakage power has become a critical research concern. To address the leakage power consumption in high-performance cache memories, a stream of novel integrated circuit and architectural level techniques are proposed by researchers including leakage-current management techniques, cell array leakage reduction techniques, bitline leakage reduction techniques, and leakage current compensation techniques. The main goal of this work was to improve the cell array leakage reduction techniques in order to minimize the leakage power for SRAM memory design in low-power applications. This study performs the body biasing application to reduce leakage current as well. To adjust the NMOSs\u27 threshold voltage and consequently leakage current, a negative DC voltage could be applied to their body terminal as a second gate. As a result, in order to generate a negative DC voltage, this study proposes a negative voltage reference that includes a trimming circuit and a negative level shifter. These enhancements are employed to a 10kb SRAM memory operating at 0.3V in a 65nm CMOS process

A CURRENT TO DIGITAL CONVERTER FOR POWER SIGNATURE GENERATION APPLICATIONS

The security of IoT devices is significantly increasing as a consequence of the widespread usage of the Internet of Things (IoT) in applications that include confidential data and implementation of important control decisions using those data. Because of their cheap cost and computational limitations, IoT devices confront significant obstacles in safeguarding. Among the variety of devised tactics analyzing power is one of the most potential strategies to address such challenges. However, due to the size, cost, and power consumption of power analysis devices, this strategy is not suited for many IoT applications. In this thesis, two techniques for collecting power signatures were proposed. A commercial 130nm CMOS technology is used to construct two circuits for each technique. For the purpose of determining how correctly the setups function, a considerable number of simulations are run under various conditions, and the results are assessed

Nano-intrinsic security primitives for internet of everything

With the advent of Internet-enabled electronic devices and mobile computer systems, maintaining data security is one of the most important challenges in modern civilization. The innovation of physically unclonable functions (PUFs) shows great potential for enabling low-cost low-power authentication, anti-counterfeiting and beyond on the semiconductor chips. This is because secrets in a PUF are hidden in the randomness of the physical properties of desirably identical devices, making it extremely difficult, if not impossible, to extract them. Hence, the basic idea of PUF is to take advantage of inevitable non-idealities in the physical domain to create a system that can provide an innovative way to secure device identities, sensitive information, and their communications. While the physical variation exists everywhere, various materials, systems, and technologies have been considered as the source of unpredictable physical device variation in large scales for generating security primitives. The purpose of this project is to develop emerging solid-state memory-based security primitives and examine their robustness as well as feasibility. Firstly, the author gives an extensive overview of PUFs. The rationality, classification, and application of PUF are discussed. To objectively compare the quality of PUFs, the author formulates important PUF properties and evaluation metrics. By reviewing previously proposed constructions ranging from conventional standard complementary metal-oxide-semiconductor (CMOS) components to emerging non-volatile memories, the quality of different PUFs classes are discussed and summarized. Through a comparative analysis, emerging non-volatile redox-based resistor memories (ReRAMs) have shown the potential as promising candidates for the next generation of low-cost, low-power, compact in size, and secure PUF. Next, the author presents novel approaches to build a PUF by utilizing concatenated two layers of ReRAM crossbar arrays. Upon concatenate two layers, the nonlinear structure is introduced, and this results in the improved uniformity and the avalanche characteristic of the proposed PUF. A group of cell readout method is employed, and it supports a massive pool of challenge-response pairs of the nonlinear ReRAM-based PUF. The non-linear PUF construction is experimentally assessed using the evaluation metrics, and the quality of randomness is verified using predictive analysis. Last but not least, random telegraph noise (RTN) is studied as a source of entropy for a true random number generation (TRNG). RTN is usually considered a disadvantageous feature in the conventional CMOS designs. However, in combination with appropriate readout scheme, RTN in ReRAM can be used as a novel technique to generate quality random numbers. The proposed differential readout-based design can maintain the quality of output by reducing the effect of the undesired noise from the whole system, while the controlling difficulty of the conventional readout method can be significantly reduced. This is advantageous as the differential readout circuit can embrace the resistance variation features of ReRAMs without extensive pre-calibration. The study in this thesis has the potential to enable the development of cost-efficient and lightweight security primitives that can be integrated into modern computer mobile systems and devices for providing a high level of security

Integrated Electronics to Control and Readout Electrochemical Biosensors for Implantable Applications

Biosensors can effectively be used to monitor multiple metabolites such as glucose, lactate, ATP and drugs in the human body. Continuous monitoring of these metabolites is essential for patients with chronic or critical conditions. Moreover, this can be used to tune the dosage of a drug for each individual patient, in order to achieve personalized therapy. Implantable medical devices (IMDs) based on biosensors are emerging as a valid alternative for blood tests in laboratories. They can provide continuous monitoring while reduce the test costs. The potentiostat plays a fundamental role in modern biosensors. A potentiostat is an electronic device that controls the electrochemical cell, using three electrodes, and runs the electrochemical measurement. In particular the IMDs require a low-power, fully-integrated, and autonomous potentiostats to control and readout the biosensors. This thesis describes two integrated circuits (ICs) to control and readout multi-target biosensors: LOPHIC and ARIC. They enable chronoamperometry and cyclic voltammetrymeasurements and consume sub-mW power. The design, implementation, characterisation, and validation with biosensors are presented for each IC. To support the calibration of the biosensors with environmental parameters, ARIC includes circuitry to measure the pHand temperature of the analyte through an Iridiumoxide pH sensor and an off-chip resistor-temperature detector (RTD). In particular, novel circuits to convert resistor value into digital are designed for RTD readout. ARIC is integrated into two IMDs aimed for health-care monitoring and personalized therapy. The control and readout of the embedded sensor arrays have been successfully achieved, thanks to ARIC, and validated for glucose and paracetamol measurements while it is remotely powered through an inductive link. To ensure the security and privacy of IMDs, a lightweight cryptographic system (LCS) is presented. This is the first ASIC implementation of a cryptosystem for IMDs, and is integrated into ARIC. The resulting system provides a unique and fundamental capability by immediately encrypting and signing the sensor data upon its creation within the body. Nano-structures such as Carbon nanotubes have been widely used to improve the sensitivity of the biosensors. However, in most of the cases, they introduce more noise into the measurements and produce a large background current. In this thesis the noise of the sensors incorporating CNTs is studied for the first time. The effect of CNTs as well as sensor geometry on the signal to noise ratio of the sensors is investigated experimentally. To remove the background current of the sensors, a differential readout scheme has been proposed. In particular, a novel differential readout IC is designed and implemented that measures inputcurrents within a wide dynamic range and produces a digital output that corresponds to the -informative- redox current of the biosensor