Low complexity physical layer security approach for 5G internet of things

Fifth-generation (5G) massive machine-type communication (mMTC) is expected to support the cellular adaptation of internet of things (IoT) applications for massive connectivity. Due to the massive access nature, IoT is prone to high interception probability and the use of conventional cryptographic techniques in these scenarios is not practical considering the limited computational capabilities of the IoT devices and their power budget. This calls for a lightweight physical layer security scheme which will provide security without much computational overhead and/or strengthen the existing security measures. Here a shift based physical layer security approach is proposed which will provide a low complexity security without much changes in baseline orthogonal frequency division multiple access (OFDMA) architecture as per the low power requirements of IoT by systematically rearranging the subcarriers. While the scheme is compatible with most fast Fourier transform (FFT) based waveform contenders which are being proposed in 5G especially in mMTC and ultra-reliable low latency communication (URLLC), it can also add an additional layer of security at physical layer to enhanced mobile broadband (eMBB)

Lightweight mutual authentication, owner transfer, and secure search protocols for RFID systems

RFID technology can potentially be applied almost everywhere. A typical RFID system involves a reader and a number of tags, which may range from the battery-powered ones with Wi-Fi capabilities, to the low-cost ones that are constrained in resources with even no internal power. Keeping RFID systems secure is important, because they are vulnerable to a number of malicious attacks. As for low-cost RFID systems, security problems become much more challenging, as many traditional security mechanisms are inefficient or even impossible due to resource constraints. Some existing solutions utilize traditional cryptographic primitives such as hash or encryption functions, which are often too expensive in hardware to be implemented on low-cost RFID tags. Furthermore, some other lightweight solutions have been reported to be broken, revealing their keys and ID numbers to the attackers. In this thesis, we propose lightweight solutions to Mutual Authentication and Ownership Transfer for RFID systems. Mutual Authentication mitigates the issues of eavesdropping and cloning of tags. Only authenticated readers and tags will successfully communicate with each other. Furthermore, we adapt our Mutual Authentication scheme to secure the Ownership Transfer of RFID tags, which is a pertinent issue in the scope of RFID. When an item passes from one owner to another, it is undesirable for the old owner to be able to access the tag or read data from it. The new user must therefore update the access-granting information without revealing this to the old owner. Tag search is another important functionality that a RFID system should provide. In this thesis, we study how to secure tag search with a focus on low-cost RFID systems for which existing solution is not efficient. These protocols are all realized by utilizing minimalistic cryptography such as Physically Unclonable Functions (PUF) and Linear Feedback Shift Registers (LFSR). PUFs and LFSRs are very efficient in hardware, and provide the low-cost RFID tags with unique characteristics that prevent a multitude of attacks. Compared to existing solutions built on top of hash functions that require 8000 - 10000 gates, our experimental results show that the schemes we propose demand only between 650 - 1400 gates for 64 bit variables and can be easily accommodated by the cheapest RFID tags with only 2000 gates available for security functions

Area and Energy Optimizations in ASIC Implementations of AES and PRESENT Block Ciphers

When small, modern-day devices surface with neoteric features and promise benefits like streamlined business processes, cashierless stores, and autonomous driving, they are all too often accompanied by security risks due to a weak or absent security component. In particular, the lack of data privacy protection is a common concern that can be remedied by implementing encryption. This ensures that data remains undisclosed to unauthorized parties. While having a cryptographic module is often a goal, it is sometimes forfeited because a device's resources do not allow for the conventional cryptographic solutions. Thus, smaller, lower-energy security modules are in demand. Implementing a cipher in hardware as an application-specific integrated circuit (ASIC) will usually achieve better efficiency than alternatives like FPGAs or software, and can help towards goals such as extended battery life and smaller area footprint. The Advanced Encryption Standard (AES) is a block cipher established by the National Institute of Standards and Technology (NIST) in 2001. It has since become the most widely adopted block cipher and is applied in a variety of applications ranging from smartphones to passive RFID tags to high performance microprocessors. PRESENT, published in 2007, is a smaller lightweight block cipher designed for low-power applications. In this study, low-area and low-energy optimizations in ASICs are addressed for AES and PRESENT. In the low-area work, three existing AES encryption cores are implemented, analyzed, and benchmarked using a common fabrication technology (STM 65 nm). The analysis includes an examination of various implementations of internal AES operations and their suitability for different architectural choices. Using our taxonomy of design choices, we designed Quark-AES, a novel 8-bit AES architecture. At 1960 GE, it features a 13% improvement in area and 9% improvement in throughput/area² over the prior smallest design. To illustrate the extent of the variations due to the use of different ASIC libraries, Quark-AES and the three analyzed designs are also synthesized using three additional technologies. Even for the same transistor size, different ASIC libraries produce significantly different area results. To accommodate a variety of applications that seek different levels of tradeoffs in area and throughput, we extend all four designs to 16-bit and 32-bit datawidths. In the low-energy work, round unrolling and glitch filtering are applied together to achieve energy savings. Round unrolling, which applies multiple block cipher rounds in a combinational path, reduces the energy due to registers but increases the glitching energy. Glitch filtering complements round unrolling by reducing the amount of glitches and their associated energy consumption. For unrolled designs of PRESENT and AES, two glitch filtering schemes are assessed. One method uses AND-gates in between combinational rounds while the other used latches. Both methods work by allowing the propagation of signals only after they have stabilized. The experiments assess how energy consumption changes with respect to the degree of unrolling, the glitch filtering scheme, the degree of pipelining, the spacing between glitch filters, and the location of glitch filters when only a limited number of them can be applied due to area constraints. While in PRESENT, the optimal configuration depends on all the variables, in a larger cipher such as AES, the latch-based method consistently offers the most energy savings

J3Gen : a PRNG for Low-Cost Passive RFID

Pseudorandom number generation (PRNG) is the main security tool in low-cost passive radio-frequency identification (RFID) technologies, such as EPC Gen2. We present a lightweight PRNG design for low-cost passive RFID tags, named J3Gen. J3Gen is based on a linear feedback shift register (LFSR) configured with multiple feedback polynomials. The polynomials are alternated during the generation of sequences via a physical source of randomness. J3Gen successfully handles the inherent linearity of LFSR based PRNGs and satisfies the statistical requirements imposed by the EPC Gen2 standard. A hardware implementation of J3Gen is presented and evaluated with regard to different design parameters, defining the key-equivalence security and nonlinearity of the design. The results of a SPICE simulation confirm the power-consumption suitability of the proposal

Robust Color Image Encryption Scheme Based on RSA via DCT by Using an Advanced Logic Design Approach

تتزايد أهمية أمن المعلومات في تخزين البيانات ونقلها. من جانب اخر يتم استخدام الصور في العديد من الإجراءات. لذلك ، يعد منع الوصول غير المصرح به إلى بيانات الصورة أمرًا بالغ الأهمية من خلال تشفير الصور لاجل حماية البيانات الحساسة او الخصوصية. تتنوع طرق وخوارزميات إخفاء الصور أو تشفيرها من طرق المجال المكاني البسيطة إلى طرق مجال التردد والذي يعتبر الأكثر تعقيدًا وموثوقية. في هذا البحث ، نقترح نظام تشفير جديد يعتمد على منهجية تهجين مولد المفتاح العشوائي من خلال الاستفادة من خصائص DCT لتوليد مجموعة غير محددة من المفاتيح العشوائية والاستفادة من معاملات المنطقة منخفضة التردد بعد مرحلة DCT لتمريرها إلى نظام فرعي يتكون من مجموعة RLG للحصول على المفاتيح السرية التي يتم تمريرها إلى RSA لتنتهي بتشفير الصورة. تشير النتائج إلى أن الطريقة المقترحة لها القدرة على تولد مجموعة كبيرة جدًا من المفاتيح السرية شديدة التعقيد والآمنة التي يمكن استخدامها لاحقًا في مرحلة التشفير. علاوة على ذلك ، سيتغير عدد وتعقيد تلك المفاتيح في كل مرة يتم فيها تغيير الصورة، وهذا يمثل مساهمة الطريقة المقترحة. ولم نلاحظ اي ضياع للوقت أثناء عمليات التشفير وفك التشفير لاستخدامنا RLG ، مما يدل على أن النظام المقترح قام بعمل جيد في صنع مفاتيح مختلفة من نفس الصورة. ويختلف في قوة المفتاح من صورة إلى أخرى حسب طبيعة الصورة الملونة.Information security in data storage and transmission is increasingly important. On the other hand, images are used in many procedures. Therefore, preventing unauthorized access to image data is crucial by encrypting images to protect sensitive data or privacy. The methods and algorithms for masking or encoding images vary from simple spatial-domain methods to frequency-domain methods, which are the most complex and reliable. In this paper, a new cryptographic system based on the random key generator hybridization methodology by taking advantage of the properties of Discrete Cosine Transform (DCT) to generate an indefinite set of random keys and taking advantage of the low-frequency region coefficients after the DCT stage to pass them to a subsystem consisting of an Reversible Logic Gate (RLG) group to obtain the secret keys that are passed to Rivest Shamir Adleman (RSA) to finish encrypting the image. The results indicate that the proposed method has the ability to generate a very large set of highly complex and secure secret keys that can be used later in the encryption stage. Moreover, the number and complexity of those keys will change each time the image is changed, and this represents the contribution of the proposed method. They experienced no time loss throughout the encryption and decryption processes when using RLG, which indicates that the proposed system did a good job in making different keys from the same image. And it differs in the strength of the key from one image to another, depending on the nature of the color imge

Lightweight PUF-Based Gate Replacement Technique to Reduce Leakage of Information through Power Profile Analysis

The major challenge faced by electronic device designers is to defend the system from attackers and malicious modules called Hardware Trojans and to deliver a secured design. Although there are many cryptographic preventive measures in place adversaries find different ways to attack the device. Differential Power Analysis (DPA) attack is a type of Side Channel Attacks, used by an attacker to analyze the power leakage in the circuit, through which the functionality of the circuit is extracted. To overcome this, a lightweight approach is proposed in this paper using, Wave Dynamic Differential Logic (WDDL) technique, without incurring any additional resource cost and power. The primary objective of WDDL is to make the power consumption constant of an entire circuit by restricting the leakage power. The alternate strategy used by an adversary is to leak the information through reverse engineering. The proposed work avoids this by using a bit sequencer and a modified butterfly PUF based randomizing architecture. A modified version of butterfly PUF is also proposed in this paper, and from various qualitative tests performed it is evident that this PUF can prevent information leakage. This work is validated on ISCAS 85, ISCAS 89 benchmark circuits and the results obtained indicate that the difference in leakage power is found to be very marginal