Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies

Thermal Aware Design Method for VCSEL-Based On-Chip Optical Interconnect

Optical Network-on-Chip (ONoC) is an emerging technology considered as one of the key solutions for future generation on-chip interconnects. However, silicon photonic devices in ONoC are highly sensitive to temperature variation, which leads to a lower efficiency of Vertical-Cavity Surface-Emitting Lasers (VCSELs), a resonant wavelength shift of Microring Resonators (MR), and results in a lower Signal to Noise Ratio (SNR). In this paper, we propose a methodology enabling thermal-aware design for optical interconnects relying on CMOS-compatible VCSEL. Thermal simulations allow designing ONoC interfaces with low gradient temperature and analytical models allow evaluating the SNR.Comment: IEEE International Conference on Design Automation and Test in Europe (DATE 2015), Mar 2015, Grenoble, France. 201

Photonic packaging: transforming silicon photonic integrated circuits into photonic devices

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Bandwidth Requirements of GPU Architectures

A new trend in chip multiprocessor (CMP) design is to incorporate graphics processing unit (GPU) cores, making them heterogeneous. GPU cores have a higher bandwidth requirement than CPU cores, as they tend to generate much more memory requests. In order to achieve good performance, there must be sufficient bandwidth between the GPU shader cores and main memory to service these memory requests in a timely manner. However, designing for the highest possible bandwidth will lead to high energy costs. The communication requirements of GPU cores must be determined in order to choose a proper interconnect. To this end, we have simulated several CUDA benchmarks with varying bandwidths using the GPGPU-Sim simulator. Our results show that the communication requirements of GPUs vary from workload to workload. We suggest that cores be connected using a photonic interconnect capable of supporting different bandwidths in order to reduce power consumption. For each transmission, the interconnect used will depend on how the bandwidth affects performance. We determined that the ratio of interconnect-shader stalls to the total number of execution cycles is a good indicator of whether or not an application will be bandwidth-sensitive. We used this finding to develop a bandwidth selection policy for GPU applications using a photonic NoC. With our policy selections, the photonic interconnect used 12.5% less power than a photonic interconnect with optimal performing choices, which only gave a performance improvement of 1.37% compared to our policy. The photonic interconnect with our policy also had the lowest energy-delay product out of the interconnects we compared it against

Metallic Coaxial Nanolasers

The last two decades have witnessed tremendous advancements in the area of nanophotonics and plasmonics. Undoubtedly, the introduction of metallic structures has opened a path towards light confinement and manipulation at the subwavelength scale { a regime that was previously thought to be out of reach in optics. Of central importance is to devise efficient light sources to power up the future nanoscale optical circuits. Coaxial resonators can provide a platform to implement such subwavelength sources. They support ultrasmall cavity modes and offer large mode-emitter overlap as well as multifold scalability. Given their large modulation bandwidth, they hold promise for high speed optical interconnects { where they can be used for light generation and modulation simultaneously. In addition, the possibility of thresholdless operation in such devices may have implications in developing the next generation of efficient lighting systems. In this review article, the physics and applications of coaxial nanolasers will be discussed