Study of First-Order Thermal Sigma-Delta Architecture for Convective Accelerometers

This paper presents the study of an original closed-loop conditioning approach for fully-integrated convective inertial sensors. The method is applied to an accelerometer manufactured on a standard CMOS technology using an auto-aligned bulk etching step. Using the thermal behavior of the sensor as a summing function, a first order sigma-delta modulator is built. This "electro-physical" modulator realizes an analog-to-digital conversion of the signal. Besides the feedback scheme should improve the sensor performance.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838

Microwave integrated circuit for Josephson voltage standards

A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained

Thermal budget of superconducting digital circuits at sub-kelvin temperatures

Superconducting single-flux-quantum (SFQ) circuits have so far been developed and optimized for operation at or above helium temperatures. The SFQ approach, however, should also provide potentially viable and scalable control and read-out circuits for Josephson-junction qubits and other applications with much lower, milli-kelvin, operating temperatures. This paper analyzes the overheating problem which becomes important in this new temperature range. We suggest a thermal model of the SFQ circuits at sub-kelvin temperatures and present experimental results on overheating of electrons and silicon substrate which support this model. The model establishes quantitative limitations on the dissipated power both for "local" electron overheating in resistors and "global" overheating due to ballistic phonon propagation along the substrate. Possible changes in the thermal design of SFQ circuits in view of the overheating problem are also discussed.Comment: 10 pages, 8 figures, submitted to J. Appl. Phy

Wideband digital phase comparator for high current shunts

A wideband phase comparator for precise measurements of phase difference of high current shunts has been developed at INRIM. The two-input digital phase detector is realized with a precision wideband digitizer connected through a pair of symmetric active guarded transformers to the outputs of the shunts under comparison. Data are first acquired asynchronously, and then transferred from on-board memory to host memory. Because of the large amount of data collected the filtering process and the analysis algorithms are performed outside the acquisition routine. Most of the systematic errors can be compensated by a proper inversion procedure. The system is suitable for comparing shunts in a wide range of currents, from several hundred of milliampere up to 100 A, and frequencies ranging between 500 Hz and 100 kHz. Expanded uncertainty (k=2) less than 0.05 mrad, for frequency up to 100 kHz, is obtained in the measurement of the phase difference of a group of 10 A shunts, provided by some European NMIs, using a digitizer with sampling frequency up to 1 MHz. An enhanced version of the phase comparator employs a new digital phase detector with higher sampling frequency and vertical resolution. This permits to decrease the contribution to the uncertainty budget of the phase detector of a factor two from 20 kHz to 100 kHz. Theories and experiments show that the phase difference between two high precision wideband digitizers, coupled as phase detector, depends on multiple factors derived from both analog and digital imprint of each sampling system.Comment: 20 pages, 9 figure

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

A novel active quenching circuit for single photon detection with Geiger mode avalanche photodiodes

In this paper we present a novel construction of an active quenching circuit intended for single photon detection. For purpose of evaluation, we have combined this circuit with a standard avalanche photodiode C30902S to form a single photon detector. A series of measurements, presented here, show that this single photon detector has a dead time of less than 40ns, maximum random counting frequency of over 14MHz, low after pulsing, detection efficiency of over 20% and a good noise performance. This simple and robust active quenching circuit can be built from of-the-shelf electronic components and needs no complicated adjustments.Comment: 9 pages, 13 figures, 15 reference

Avalanche photodiode photon counting receivers for space-borne lidars

Avalanche photodiodes (APD) are studied for uses as photon counting detectors in spaceborne lidars. Non-breakdown APD photon counters, in which the APD's are biased below the breakdown point, are shown to outperform: (1) conventional APD photon counters biased above the breakdown point; (2) conventional APD photon counters biased above the breakdown point; and (3) APD's in analog mode when the received optical signal is extremely weak. Non-breakdown APD photon counters were shown experimentally to achieve an effective photon counting quantum efficiency of 5.0 percent at lambda = 820 nm with a dead time of 15 ns and a dark count rate of 7000/s which agreed with the theoretically predicted values. The interarrival times of the counts followed an exponential distribution and the counting statistics appeared to follow a Poisson distribution with no after pulsing. It is predicted that the effective photon counting quantum efficiency can be improved to 18.7 percent at lambda = 820 nm and 1.46 percent at lambda = 1060 nm with a dead time of a few nanoseconds by using more advanced commercially available electronic components

The Modern FPGA as Discriminator, TDC and ADC

Recent generations of Field Programmable Gate Arrays (FPGAs) have become indispensible tools for complex state machine control and signal processing, and now routinely incorporate CPU cores to allow execution of user software code. At the same time, their exceptional performance permits low-power implementation of functionality previously the exclusive domain of dedicated analog electronics. Specific examples presented here use FPGAs as discriminator, time-to-digital (TDC) and analog-to-digital converter (ADC). All three cases are examples of instrumentation for current or future astroparticle experiments.Comment: 7 pages, v3 minor JINST editorial correction