Interfacing of artificial hairs array for complex flow pattern recognition

In this paper we report on the latest developments in characterising and interfacing biomimetic flow-sensor array based on the flow sensitive mechano-sensors of crickets. Capacitive hair sensors have been fabricated using a surface micromachining technology and implemented to detect air flows. We have realized readout electronics to detect the movements capacitively using electrodes integrated on the membrane. A charge amplifier, which produces an output voltage representing the capacitance variation of the selected sensor, is used to pick up the signal. An array of hair sensors is implemented for better and more representative flow signals compared to single sensor measurement. Different schemes for measuring individual sensors in arrays independently are discussed. Frequency Division Multiplexing is found to be efficient for this purpose individual element measurement.\ud Key Words: Artificial hairs, capacitive readout, FD

A Closed-loop capacitance to pulse-width converter for single element capacitive sensors

A novel closed-loop capacitance-to-pulse width converter (CPC) suitable for single element capacitive sensors that use sinusoidal excitation is presented in this paper. Its operation is realized using a new configuration based on a simple, yet effective, auto-balancing scheme. The hardware prototype of the proposed CPC is relatively less complex to implement than those presented so far in the literature. It provides a quasi-digital output at a high update rate. Additionally, the output is insensitive to parasitic capacitances of the sensor. The output possesses high linearity, with respect to change in the sensor capacitance, ranging +/-5 pF, with a nominal capacitance as high as 200 pF. It exhibits a maximum non-linearity error of 0.061%FS. The output of the prototype has a resolution of 13.31 bits. Also, its response time for a step-change in the sensor capacitance is about 13 ms. This sophisticated and inexpensive closed-loop CPC is a perfect fit as an interfacing circuit for single element capacitive sensors.Peer ReviewedPostprint (author's final draft

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

An auto-balancing capacitance-to-pulse-width converter for capacitive sensors

A novel auto-balancing capacitance-to-pulse- width converter (CPC) that uses sinusoidal excitation, and operates in a closed-loop configuration, is presented in this paper. Unlike most of the existing CPCs, the proposed interface circuit is compatible with both single-element and differential capacitive sensors. In addition, it provides a pulse-width modulated (PWM) signal which can easily be digitized using a counter. From this PWM signal, a ratio output is derived when a single-element sensor is interfaced, and a ratiometric output is obtained for a differential sensor.The authors would like to thank the Department of Science and Technology (DST), Govt. of India, for its financial assistance (Grant Number SERB/F/4573/2016-17) in carrying out the research activities presented in this paper.Postprint (published version

Compensated Current Injection circuit, theory and applications

This paper presents a detailed description, analysis and example of practical application of a wide frequency band voltage-to-current converter. The converter is characterized by a combination of positive and negative feedback loops. This feature allows compensation for parasitic impedance connected in parallel with the useful load, which in turn keeps an excitation current flowing through the useful load independent of its impedance. The simplicity of the circuit and its good electrical properties are additional advantages of the scheme.Comment: 9 pages and 7 figures in one PDF fil

Comparison of Two Low-Power Electronic Interfaces for Capacitive Mems Sensors

The paper discusses the importance and the issues of interfacing capacitive sensors. Two architectures applicable for interfacing capacitive sensors are presented. The first solution was designed to interface a capacitive humidity sensor designed and built for a humidity-dependent monolithic capacitor developed at Budapest University of Technology and Economics. The second case presents the possible read-out solutions for a SOI-MEMS accelerometer. Both of the architectures were built and tested in a discrete implementation to qualify the methods before the integrated realization. The paper presents a detailed comparison of the two methodsComment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/EDA-Publishing

A Fully Differential CMOS Potentiostat

A CMOS potentiostat for chemical sensing in a noisy environment is presented. The potentiostat measures bidirectional electrochemical redox currents proportional to the concentration of a chemical down to pico-ampere range. The fully differential architecture with differential recording electrodes suppresses the common mode interference. A 200μm×200μm prototype was fabricated in a standard 0.35μm standard CMOS technology and yields a 70dB dynamic range. The in-channel analog-to-digital converter (ADC) performs 16-bit current-tofrequency quantization. The integrated potentiostat functionality is validated in electrical and electrochemical experiments

An efficient tool for the assisted design of SAR ADCs capacitive DACs

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10^4 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics