X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Silicon-based Static Random Access Memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying \textit{von-Neumann} computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-art computing systems, to a large extent, results from the well-known \textit{von-Neumann bottleneck}. The energy and throughput inefficiency of the von-Neumann machines have been accentuated in recent times due to the present emphasis on data-intensive applications like artificial intelligence, machine learning \textit{etc}. A possible approach towards mitigating the overhead associated with the von-Neumann bottleneck is to enable \textit{in-memory} Boolean computations. In this manuscript, we present an augmented version of the conventional SRAM bit-cells, called \textit{the X-SRAM}, with the ability to perform in-memory, vector Boolean computations, in addition to the usual memory storage operations. We propose at least six different schemes for enabling in-memory vector computations including NAND, NOR, IMP (implication), XOR logic gates with respect to different bit-cell topologies $-$ the 8T cell and the 8$^+$T Differential cell. In addition, we also present a novel \textit{`read-compute-store'} scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using predictive transistor models and Monte-Carlo variation analysis.Comment: This article has been accepted in a future issue of IEEE Transactions on Circuits and Systems-I: Regular Paper

A new coupling solution for G3-PLC employment in MV smart grids

This paper proposes a new coupling solution for transmitting narrowband multicarrier power line communication (PLC) signals over medium voltage (MV) power lines. The proposed system is based on an innovative PLC coupling principle, patented by the authors, which exploits the capacitive divider embedded in voltage detecting systems (VDS) already installed inside the MV switchboard. Thus, no dedicated couplers have to be installed and no switchboard modifications or energy interruptions are needed. This allows a significant cost reduction of MV PLC implementation. A first prototype of the proposed coupling system was presented in previous papers: it had a 15 kHz bandwidth useful to couple single carrier PSK modulated PLC signals with a center frequency from 50–200 kHz. In this paper, a new prototype is developed with a larger bandwidth, up to 164 kHz, thus allowing to couple multicarrier G3-PLC signals using orthogonal frequency division multiplexing (OFDM) digital modulation. This modulation ensures a more robust communication even in harsh power line channels. In the paper, the new coupling system design is described in detail. A new procedure is presented for tuning the coupling system parameters at first installation in a generic MV switchboard. Finally, laboratory and in-field experimental test results are reported and discussed. The coupling performances are evaluated measuring the throughput and success rate in the case of both 18 and 36 subcarriers, in one of the different tone masks standardized for the FCC-above CENELEC band (that is, from 154.6875–487.5 kHz). The experimental results show an efficient behavior of the proposed coupler allowing a two-way communication of G3-PLC OFDM signals on MV networks