268 research outputs found
Accelerate & Actualize: Can 2D Materials Bridge the Gap Between Neuromorphic Hardware and the Human Brain?
Two-dimensional (2D) materials present an exciting opportunity for devices
and systems beyond the von Neumann computing architecture paradigm due to their
diversity of electronic structure, physical properties, and atomically-thin,
van der Waals structures that enable ease of integration with conventional
electronic materials and silicon-based hardware. All major classes of
non-volatile memory (NVM) devices have been demonstrated using 2D materials,
including their operation as synaptic devices for applications in neuromorphic
computing hardware. Their atomically-thin structure, superior physical
properties, i.e., mechanical strength, electrical and thermal conductivity, as
well as gate-tunable electronic properties provide performance advantages and
novel functionality in NVM devices and systems. However, device performance and
variability as compared to incumbent materials and technology remain major
concerns for real applications. Ultimately, the progress of 2D materials as a
novel class of electronic materials and specifically their application in the
area of neuromorphic electronics will depend on their scalable synthesis in
thin-film form with desired crystal quality, defect density, and phase purity.Comment: Neuromorphic Computing, 2D Materials, Heterostructures, Emerging
Memory Devices, Resistive, Phase-Change, Ferroelectric, Ferromagnetic,
Crossbar Array, Machine Learning, Deep Learning, Spiking Neural Network
Exploration of Mutli-Threshold Ferro-Electric FET Based Designs
The surge in data intensive applications has given rise to demand for high density storage devices and their efficient implementations. Consequently, Multi-level-cell(MLC) memories are getting explored for their promising aspects of higher storage density and lower unit storage cost. However, the multi-bit data stored in these memories need to be converted to processor compatible forms (typically binary) for processing. In this work, we have proposed an adaptable multi-level voltage to binary converter using Ferro-electric Field Effect Transistors(FeFET) capable of translating input voltage to bits. The use of FeFETs as voltage comparators simplifies the circuit and offers adaptable voltage quantization, flexible output bit-width(1/2 bits) and security feature. The circuit also employs incremental output encoding, which limits error margin to the least significant bits(LSB). The proposed 4-level to 2-bit converter circuit is demonstrated in simulation to have an input voltage range of [0 ? 3.75V] / [0 ? 2.7V] for FeFETs with 20/2000-domains respectively
FeFET-based Binarized Neural Networks Under Temperature-dependent Bit Errors
Ferroelectric FET (FeFET) is a highly promising emerging non-volatile memory (NVM) technology, especially for binarized neural network (BNN) inference on the low-power edge. The reliability of such devices, however, inherently depends on temperature. Hence, changes in temperature during run time manifest themselves as changes in bit error rates. In this work, we reveal the temperature-dependent bit error model of FeFET memories, evaluate its effect on BNN accuracy, and propose countermeasures. We begin on the transistor level and accurately model the impact of temperature on bit error rates of FeFET. This analysis reveals temperature-dependent asymmetric bit error rates. Afterwards, on the application level, we evaluate the impact of the temperature-dependent bit errors on the accuracy of BNNs. Under such bit errors, the BNN accuracy drops to unacceptable levels when no countermeasures are employed. We propose two countermeasures: (1) Training BNNs for bit error tolerance by injecting bit flips into the BNN data, and (2) applying a bit error rate assignment algorithm (BERA) which operates in a layer-wise manner and does not inject bit flips during training. In experiments, the BNNs, to which the countermeasures are applied to, effectively tolerate temperature-dependent bit errors for the entire range of operating temperature
Content Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing
As a promising alternative to the Von Neumann architecture, in-memory
computing holds the promise of delivering high computing capacity while
consuming low power. Content addressable memory (CAM) can implement pattern
matching and distance measurement in memory with massive parallelism, making
them highly desirable for data-intensive applications. In this paper, we
propose and demonstrate a novel 1-transistor-per-bit CAM based on the
ferroelectric reconfigurable transistor. By exploiting the switchable polarity
of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching
operation in CAM can be realized in a single transistor. By eliminating the
need for the complementary circuit, these non-volatile CAMs based on
reconfigurable transistors can offer a significant improvement in area and
energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs
are also demonstrated, which enable multi-bit matching in a single reading
operation. In addition, the NOR array of CAM cells effectively measures the
Hamming distance between the input query and stored entries. Furthermore,
utilizing the switchable polarity of these ferroelectric Schottky barrier
transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual
functions, whose input-output mapping can be transformed in real-time without
changing the layout. These reconfigurable circuits will serve as important
building blocks for high-density data-stream processors and reconfigurable
Application-Specific Integrated Circuits (r-ASICs). The CAMs and transformable
logic gates based on ferroelectric reconfigurable transistors will have broad
applications in data-intensive applications from image processing to machine
learning and artificial intelligence
Analog Content-Addressable Memory from Complementary FeFETs
To address the increasing computational demands of artificial intelligence
(AI) and big data, compute-in-memory (CIM) integrates memory and processing
units into the same physical location, reducing the time and energy overhead of
the system. Despite advancements in non-volatile memory (NVM) for matrix
multiplication, other critical data-intensive operations, like parallel search,
have been overlooked. Current parallel search architectures, namely
content-addressable memory (CAM), often use binary, which restricts density and
functionality. We present an analog CAM (ACAM) cell, built on two complementary
ferroelectric field-effect transistors (FeFETs), that performs parallel search
in the analog domain with over 40 distinct match windows. We then deploy it to
calculate similarity between vectors, a building block in the following two
machine learning problems. ACAM outperforms ternary CAM (TCAM) when applied to
similarity search for few-shot learning on the Omniglot dataset, yielding
projected simulation results with improved inference accuracy by 5%, 3x denser
memory architecture, and more than 100x faster speed compared to central
processing unit (CPU) and graphics processing unit (GPU) per similarity search
on scaled CMOS nodes. We also demonstrate 1-step inference on a kernel
regression model by combining non-linear kernel computation and matrix
multiplication in ACAM, with simulation estimates indicating 1,000x faster
inference than CPU and GPU
Investigating ferroelectric and metal-insulator phase transition devices for neuromorphic computing
Neuromorphic computing has been proposed to accelerate the computation for deep neural networks (DNNs). The objective of this thesis work is to investigate the ferroelectric and metal-insulator phase transition devices for neuromorphic computing. This thesis proposed and experimentally demonstrated the drain erase scheme in FeFET to enable the individual cell program/erase/inhibition for in-situ training in 3D NAND-like FeFET array. To achieve multi-level states for analog in-memory computing, the ferroelectric thin film needs to be partially switched. This thesis identified a new challenge of ferroelectric partial switching, namely “history effect” in minor loop dynamics. The experimental characterization of both FeCap and FeFET validated the history effect, suggesting that the intermediate states programming condition depends on the prior states that the device has gone through. A phase-field model was constructed to understand the origin. Such history effect was then modelled into the FeFET based neural network simulation and analyze its negative impact on the training accuracy and then propose a possible mitigation strategy. Apart from using FeFET as synaptic devices, using metal-insulator phase transition device, as neuron was also explored experimentally. A NbOx metal-insulator phase transition threshold switch was integrated at the edge of the crossbar array as an oscillation neuron. One promising application for FeFET+NbOx neuromorphic system is to implement quantum error correction (QEC) circuitry at 4K. Cryo-NeuroSim, a device-to-system modeling framework that calibrates data at cryogenic temperature was developed to benchmark the performance of the FeFET+NbOx neuromorphic system.Ph.D
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