Design of High Speed Comparator

A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog - to - digital converters with High Spee d, low power dissipation and immune to. Back - to - back inverter in the latch stage is replaced with dual - input single output differential amplifier. This topology completely removes the noise that is present in the input. The stru cture shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current source ces, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, n oise immunity

An Offset Cancelation Technique for Latch Type Sense Amplifiers

An offset compensation technique for a latch type sense amplifier is proposed in this paper. The proposed scheme is based on the recalibration of the charging/discharging current of the critical nodes which are affected by the device mismatches. The circuit has been designed in a 65 nm CMOS technology with 1.2 V core transistors. The auto-calibration procedure is fully digital. Simulation results are given verifying the operation for sampling a 5 Gb/s signal dissipating only 360 uW

Analysis and Design of Power Gated Low-Power, High Performance Latch Dynamic Double-Tail Comparator

This paper introduces an elite, low power dynamic hook comparator making utilization of energy gating system with the end goal of diminished power. The comparator has dependably been a heart of simple to advanced converters in VLSI circuits. The lessening in power utilization of comparator eventually diminishes the power utilization in ADC squares. The proposed configuration has been recreated on Tanner EDA at 180nm TSMC and accomplished up to 15% diminishment in power and 71% lessening on kickback clamour from the traditional plans and in view of the present outcomes and investigation. A new low power, elite comparator is proposed, where the circuit of a dynamic twofold tail comparator with power gating procedure is altered for low-power and quick operation even in little supply voltages. With no troubles in circuit plan and by including couple of transistors, the positive criticism amid the recovery is reinforced, which brings about amazingly lessened defer time. Post-design re-enactment brings about a 180nm CMOS innovation gave the examination comes about successfully. It is demonstrated that in the proposed dynamic comparator both the power utilization, defer time, kickback noise is altogether decreased

A 0.2pJ/conversion-step 6-bit 200MHz flash ADC with redundancy

Comunicación presentada al "27th Conference on Design of Circuits and Integrated Systems (DCIS 2012)" celebrada del 28 al 30 de Noviembre del 2012 en Avignon (Francia), organizada por el LIRMM laboratory of Montpellier: http://www.lirmm.fr/dcis2012/index.phpIn this paper, a 200MHz 6-bit Flash analog-to-digital converter (ADC) is presented. The principal objective is to obtain a digital-friendly converter. Hence, small and simple latched comparators are used and redundancy allows reducing the offset down to an acceptable level. This obviously requires calibration but reduces power consumption, since small size transistors can be used and the unused comparators are powered down. The proposed ADC is designed in UMC 0:18m CMOS technology. Full electrical simulations show that the ADC reaches an effective number of bits (ENOB) of 5.3 associated to a signal-to-noise-anddistortion ratio (SNDR) is 33dB. The converter consumes only 1.56mW and has figure-of-merit (FoM) of 0.2 pJ / conversion step.This work has been partially funded by the Junta de Andalucia project P09-TIC-5386, the Ministerio de Economia y Competitividad project TEC2011-28302, both of them cofinanced by the FEDER program.Peer Reviewe

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties;\ud a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design

The impact of CMOS scaling projected on a 6b full-Nyquist non-calibrated flash ADC

A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design

A Review on Digital Pixel Sensors

Digital pixel sensor (DPS) has evolved as a pivotal component in modern imaging systems and has the potential to revolutionize various fields such as medical imaging, astronomy, surveillance, IoT devices, etc. Compared to analog pixel sensors, the DPS offers high speed and good image quality. However, the introduced intrinsic complexity within each pixel, primarily attributed to the accommodation of the ADC circuit, engenders a substantial increase in the pixel pitch. Unfortunately, such a pronounced escalation in pixel pitch drastically undermines the feasibility of achieving high-density integration, which is an obstacle that significantly narrows down the field of potential applications. Nonetheless, designing compact conversion circuits along with strategic integration of 3D architectural paradigms can be a potential remedy to the prevailing situation. This review article presents a comprehensive overview of the vast area of DPS technology. The operating principles, advantages, and challenges of different types of DPS circuits have been analyzed. We categorize the schemes into several categories based on ADC operation. A comparative study based on different performance metrics has also been showcased for a well-rounded understanding

Low-Power Sliding Correlation CMOS UWB Pulsed Radar Receiver for Motion Detection

This paper presents a low-power coherent receiver for UWB pulsed Radar for motion detection. Due to accuracy of the radar motion detection, coherent detection scheme is adopted in the receiver. To relax the stringent requirement of timing synchronization, sliding correlation detection is proposed. The clocking step which determines detection resolution is determined by 2ns which is half of a pulse width or equivalent to 30cm. Receiver is designed in 0.13-μm CMOS process from 1.5 V supply. The pulse center frequency is 4GHz. The receiver includes a high voltage gain L3A, a analog correlator, a sampling comparator and a Flip Flop. The wholereceiver excluding an L3A consumes 0.9 mA of DC current and 10pJ/pulse