73 research outputs found
System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits
This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand
(UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits.
The MultiBand OFDM (MB-OFDM) proposal for UWB communications has
received significant attention for the implementation of very high data rate (up to
480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion
quadrature mixer, and the overall radio system-level design are proposed for
an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented
in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with
interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in
quadrature with fast hopping, and a linear phase baseband section with 42dB of gain
programmability. The receiver IC mounted on a FR-4 substrate provides a maximum
gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a
2.5V supply.
Two BIT techniques for analog and RF circuits are developed. The goal is to reduce
the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the
magnitude and phase responses at different nodes of an analog circuit. A complete
prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is
demonstrated by performing frequency response measurements in a range of 1 to
130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF
RMS Detector and a methodology for its use in the built-in measurement of the gain and
1dB compression point of RF circuits are proposed to address the problem of on-chip
testing at RF frequencies. The proposed device generates a DC voltage proportional to
the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology
presents and input capacitance <15fF and occupies and area of 0.03mm2. The application
of these two techniques in combination with a loop-back test architecture significantly
enhances the testability of a wireless transceiver system
Design and implementation of frequency synthesizers for 3-10 ghz mulitband ofdm uwb communication
The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB)
communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s
wireless communications. Frequency synthesis in these communication systems involves
great challenges such as high frequency and wideband operation in addition to stringent
requirements on frequency hopping time and coexistence with other wireless standards.
This research proposes frequency generation schemes for such radio systems and their
integrated implementations in silicon based technologies. Special emphasis is placed on
efficient frequency planning and other system level considerations for building compact
and practical systems for carrier frequency generation in an integrated UWB radio.
This work proposes a frequency band plan for multiband OFDM based UWB
radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency
synthesizers are designed, implemented and tested making them one of the first
frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are
implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband
(SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much
less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz
packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of
2.25 mm2.
Finally, an architecture for a UWB synthesizer is proposed that is based on a
single multiband quadrature VCO, a programmable integer divider with 50% duty cycle
and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the
tuning range requirement of the multiband VCO and leads to a very digitally intensive
architecture for wideband frequency synthesis suitable for implementation in deep
submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while
consuming 90 mW. This architecture provides an efficient solution in terms of area and
power consumption with very low complexity
Design and implementation of frequency synthesizers for 3-10 ghz mulitband ofdm uwb communication
The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB)
communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s
wireless communications. Frequency synthesis in these communication systems involves
great challenges such as high frequency and wideband operation in addition to stringent
requirements on frequency hopping time and coexistence with other wireless standards.
This research proposes frequency generation schemes for such radio systems and their
integrated implementations in silicon based technologies. Special emphasis is placed on
efficient frequency planning and other system level considerations for building compact
and practical systems for carrier frequency generation in an integrated UWB radio.
This work proposes a frequency band plan for multiband OFDM based UWB
radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency
synthesizers are designed, implemented and tested making them one of the first
frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are
implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband
(SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much
less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz
packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of
2.25 mm2.
Finally, an architecture for a UWB synthesizer is proposed that is based on a
single multiband quadrature VCO, a programmable integer divider with 50% duty cycle
and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the
tuning range requirement of the multiband VCO and leads to a very digitally intensive
architecture for wideband frequency synthesis suitable for implementation in deep
submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while
consuming 90 mW. This architecture provides an efficient solution in terms of area and
power consumption with very low complexity
An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers
Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThe rapid growth of wireless communications and the massive use of wireless end-user
equipments have created a demand for low-cost, low-power and low-area devices with
tight specifications imposed by standards. The advances in CMOS technology allows,
nowadays, designers to implement circuits that work at high-frequencies, thus, allowing
the complete implementation of RF front ends in a single chip.
In this work, a co-design strategy for the implementation of a fully integrated CMOS
receiver for use in the ISM band is presented. The main focus is given to the Mixer and
the ADC blocks of the presented architecture.
The traditional approach used in RF design requires 50
matching buffers and networks
and AC coupling capacitors between Mixer inputs and LNA and LO outputs. The codesign
strategy avoids the use of DC choke inductors for Mixer biasing, because it is
possible to use the DC level from the output of the LNA and the LO to provide bias to
the Mixer. Moreover, since the entire circuit is in the same chip and the Mixer inputs
are transistors gates, we should consider voltage instead of power and avoid the 50
matching networks.
The proposed ADC architecture relies on a 4-bit flash converter. The main goals are to
achieve low-power and high sampling frequency. To meet these goals, parametric amplification
based on MOS varactors is applied to reduce the offset voltage of the comparators,
avoiding the traditional and power-consuming approach of active pre-amplification gain
stages
An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems
The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works
Radio frequency circuits for wireless receiver front-ends
The beginning of the 21st century sees great development and demands on wireless communication technologies. Wireless technologies, either based on a cable replacement or on a networked environment, penetrate our daily life more rapidly than ever. Low operational power, low cost, small form factor, and function diversity are the crucial requirements for a successful wireless product. The receiver??s front-end circuits play an important role in faithfully recovering the information transmitted through the wireless channel.
Bluetooth is a short-range cable replacement wireless technology. A Bluetooth receiver architecture was proposed and designed using a pure CMOS process. The front-end of the receiver consists of a low noise amplifier (LNA) and mixer. The intermediate frequency was chosen to be 2MHz to save battery power and alleviate the low frequency noise problem. A conventional LNA architecture was used for reliability. The mixer is a modified Gilbert-cell using the current bleeding technique to further reduce the low frequency noise. The front-end draws 10 mA current from a 3 V power supply, has a 8.5 dB noise figure, and a voltage gain of 25 dB and -9 dBm IIP3.
A front-end for dual-mode receiver is also designed to explore the capability of a multi-standard application. The two standards are IEEE 802.11b and Bluetooth. They work together making the wireless experience more exciting. The front-end is designed using BiCMOS technology and incorporating a direct conversion receiver architecture. A number of circuit techniques are used in the front-end design to achieve optimal results. It consumes 13.6 mA from a 2.5 V power supply with a
5.5 dB noise figure, 33 dB voltage gain and -13 dBm IIP3.
Besides the system level contributions, intensive studies were carried out on the development of quality LNA circuits. Based on the multi-gated LNA structure, a CMOS LNA structure using bipolar transistors to provide linearization is proposed. This LNA configuration can achieve comparable linearity to its CMOS multi-gated counterpart and work at a higher frequency with less power consumption. A LNA using an on-chip transformer source degeneration is proposed to realize input impedance matching. The possibility of a dual-band cellular application is studied. Finally, a study on ultra-wide band (UWB) LNA implementation is performed to explore the possibility and capability of CMOS technology on the latest UWB standard for multimedia applications
High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications
The prevalence of wireless standards and the introduction of dynamic
standards/applications, such as software-defined radio, necessitate the next generation
wireless devices that integrate multiple standards in a single chip-set to support a variety
of services. To reduce the cost and area of such multi-standard handheld devices,
reconfigurability is desirable, and the hardware should be shared/reused as much as
possible. This research proposes several novel circuit topologies that can meet various
specifications with minimum cost, which are suited for multi-standard applications. This
doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the
RF front-end; and 2. The analog-to-digital converter (ADC).
The first part of this dissertation focuses on LNA noise reduction and linearization
techniques where two novel LNAs are designed, taped out, and measured. The first LNA,
implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm
CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an
inductor connected at the gate of the cascode transistor and the capacitive cross-coupling
to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and
voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power
consumption. The second LNA, implemented in UMC (United Microelectronics
Corporation) 0.13Cm CMOS process, features a practical linearization technique for
high-frequency wideband applications using an active nonlinear resistor, which obtains a
robust linearity improvement over process and temperature variations. The proposed
linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB
over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior
published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized
UWB LNA achieves excellent linearity with much less power than previously published
works.
The second part of this dissertation developed a reconfigurable ADC for multistandard
receiver and video processors. Typical ADCs are power optimized for only one
operating speed, while a reconfigurable ADC can scale its power at different speeds,
enabling minimal power consumption over a broad range of sampling rates. A novel
ADC architecture is proposed for programming the sampling rate with constant biasing
current and single clock. The ADC was designed and fabricated using UMC 90nm
CMOS process and featured good power scalability and simplified system design. The
programmable speed range covers all the video formats and most of the wireless
communication standards, while achieving comparable Figure-of-Merit with customized
ADCs at each performance node. Since bias current is kept constant, the reconfigurable
ADC is more robust and reliable than the previous published works
Design of frequency synthesizers for short range wireless transceivers
The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts
Bluetooth/WLAN receiver design methodology and IC implementations
Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum.
A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed.
In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps.
Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm
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