2,864 research outputs found
Analytical model of nanowire FETs in a partially ballistic or dissipative transport regime
The intermediate transport regime in nanoscale transistors between the fully
ballistic case and the quasi equilibrium case described by the drift-diffusion
model is still an open modeling issue. Analytical approaches to the problem
have been proposed, based on the introduction of a backscattering coefficient,
or numerical approaches consisting in the MonteCarlo solution of the Boltzmann
transport equation or in the introduction of dissipation in quantum transport
descriptions. In this paper we propose a very simple analytical model to
seamlessly cover the whole range of transport regimes in generic quasi-one
dimensional field-effect transistors, and apply it to silicon nanowire
transistors. The model is based on describing a generic transistor as a chain
of ballistic nanowire transistors in series, or as the series of a ballistic
transistor and a drift-diffusion transistor operating in the triode region. As
an additional result, we find a relation between the mobility and the mean free
path, that has deep consequences on the understanding of transport in nanoscale
devices
UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation
Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Ultra thin body (UTB) SOI MOSFETs are expected to replace conventional MOSFETs for integrated memory applications due to superior electrostatic integrity and better resistant to some of the sources of intrinsic parameter fluctuations. To fully realise the performance benefits of UTB SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into the compact model is developed. The impact on 6T SRAM static noise margin characteristics of discrete random dopants in the source/drain regions and body-thickness variations has been investigated for well scaled devices with physical channel length in the range of 10nm to 5nm. A comparison with the behaviour of a 6T SRAM based on a conventional 35nm MOSFET is also presented
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