A 40-GHz Load Modulated Balanced Power Amplifier using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS

© 2023 IEEE - All rights reserved. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSI.2023.3282731 ​​​​​​​In this work, a ten-way power-combined poweramplifier is designed using a load modulated balanced amplifier(LMBA)-based architecture. To provide the required magnitudeand phase controls between the main and control-signal paths ofthe LMBA, an unequal power splitter and a phase compensationnetwork are proposed. As proof of concept, the designed poweramplifier is implemented in a 45-nm SOI CMOS process. At 40GHz, it delivers a 25.1 dBm Psat with a peak power-addedefficiency (PAE) of 27.9%. At 6-dB power back-off level, itachieves 1.39 times drain efficiency enhancement over an idealClass-B power amplifier. Using a 200-MHz single-carrier 64-QAMsignal, the designed amplifier delivers an average output power of16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB andACPR of -25.3 dBc. The die size, including all testing pads, is only1.92 mm2. To the best of the authors’ knowledge, compared withthe other recently published silicon-based LMBAs, this designachieves the highest Psat.Peer reviewe

A 39-GHz Doherty-Like Power Amplifier with 22-dBm Output Power and 21% Power-Added Efficiency at 6-dB Power Back-Off

© 2024, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This is the accepted manuscript version of a conference paper which has been published in final form at https://doi.org/10.1109/JETCAS.2024.3351075The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical loadmodulated balanced amplifier (S-LMBA) architecture. This design is advantageous in minimizing the undesired impedance interaction often encountered in the classic LMBA approach. Such interactions are typically due to the use of a non-50 Ω load at the isolation port of the output quadrature coupler. Moreover, magnitude and phase control networks are carefully designed to generate the specific magnitude and phase information for the designed S-LMBA. To demonstrate the proposed ideas, the SLMBA is fabricated in a 45-nm CMOS SOI technology. At 39 GHz, a 22.1 dBm saturated output power (Psat) with a maximum poweradded efficiency (PAE) of 25.7% is achieved. In addition, 1.68 times drain efficiency enhancement is obtained over an ideal Class-B operation, when the designed S-LMBA is operated at 6 dB power back-off. An average output power of 13.1 dBm with a PAE of 14.4% at an error vector magnitude (EVMrms) above -22.5 dB and adjacent channel power ratio (ACPR) of -23 dBc is also achieved, when a 200 MHz single carrier 64-quadratureamplitude- modulation (QAM) signal is used. Including all testing pads, the footprint of the designed S-LMBA is only 1.56 mm2.Peer reviewe

Millimetre Wave Series Connected Doherty PA Using 45nm SOI Process

With the high demand for high data rate communication systems, it is expected that wireless networks will migrate into the unexploited millimeter-wave frequencies. This migration and the utilization of wide-band digitally modulated signal possessing of high Peak-to-Average-Power- Ratio (PAPR) brings diffcult challenges in attaining a satisfactory trade-off between linearity and efficiency when designing mm-wave power amplifiers (PAs). There are various methods of maximizing the output power and peak effciency of mm-wave PAs that use deep-sub-micron technologies. Of these methods, little attention has been given to the efficiency enhancement of PAs in back-off region. The use of the Doherty technique in the mm-wave frequencies has attracted little attention. This is mainly due to complexity in realizing the quarter-wave impedance inverter and the low-gain of the class-C operating peaking transistor using deep-sub-micron technologies. In this thesis, a series-connected-load (SCL) Doherty topology is proposed to enhance the efficiency of a millimeter-wave power amplifier realized on a deep-sub-micron semiconductor technology. The output combiner is determined by the ABCD matrices of the ideal combiner network in the SCL Doherty PA to ensure proper load modulation. Then, it describes the methodology applied to realize the transformer-based combiner networks while absorbing the parasitic capacitance of the transistors to maximize efficiency in the back-off region. This methodology is then applied to realize a two-stage SCL Doherty PA in 45 nm Silicon-on- Insulator CMOS technology to operate at 60 GHz

High-Efficiency Millimeter-Wave Front-Ends for Large Phased-Array Transmitters

The ever-increasing demand for wireless broadband connectivity requires infrastructure capable of supporting data transfer rates at multi-Gbps. To accommodate such heavy traffic, the channel capacity for the given spectrum must be utilized as efficiently as possible. Wideband millimeter-wave phased-array systems can enhance the capacity of the channel by providing multiple steerable directional beams. However the cost, complexity, and high power consumption of phased-array systems are key barriers to the commercialization of such technology. Silicon-based beam-former chips and scalable phased-array technology offer promising solutions to lower the cost of phased-array systems. However, the implementation of low-power phased-array architectures is still a challenge. Millimeter-wave power generation in silicon beam-formers suffers from low efficiency. The stringent linearity requirements for multi-beam wideband arrays further limits the achievable efficiency. In scalable phased-arrays, each module consists of an antenna sub-array and a beam-former chip that feeds the antenna elements. To improve efficiency, a design methodology that considers the beam-former chip and the antenna array as one entity is necessary. In this thesis, power-efficient solutions for a millimeter-wave phased-array transmitter are studied and different high-efficiency power amplifier structures for broadband applications are proposed. Initially, the design of a novel 27-30 GHz RF front-end consisting of a variable gain amplifier, a 360 degree phase shifter, and a two-stage linear power amplifier with output power of 12 dBm is described. It is fabricated using 0.13 $\mu m$ SiGe technology. This chip serves as the RF core of a beam-former chip with eight outputs for feeding a 2$\times$2 dual-feed sub-array. Such sub-arrays are used as part of large phased-arrays for SATCOM infrastructure. Measurement results show 26.7 \% total efficiency for the designed chip. The chip achieves the highest efficiency among Ka-band phased-array transmitters reported in the literature. In addition, original transformer-based output matching structures are proposed for harmonic-tuned power amplifiers. Harmonic-tuned power amplifiers have high peak-efficiency but their complicated output matching structure can limit their use in beam-former RF front-ends. The proposed output matching structures have the layout footprint of a transformer, making their use in beam-former chips feasible. A 26-38 GHz power amplifier based on a non-inverting 1:1 transformer is fabricated. A measured efficiency of more than 27 \% is achieved across the band with an output power of 12 dBm. Furthermore, two continuous class $F^{-1}$ power amplifiers using 1:1 inverting transformers are described. Simulation results show a peak-efficiency of 35 \% and output power of 12 dBm from 24 to 30 GHz. A common-base power amplifier with inverting transformer output matching is also demonstrated. This amplifier achieves a peak-efficiency of 42 \% and peak output power of 16 dBm. Finally, a low-loss Ka-band re-configurable output matching structure based on tunable lines is proposed and implemented. A double-stub matching structure with three tunable segments is proposed to maximize the impedance matching coverage. This structure can potentially compensate for the antenna impedance variation in phased-array antennas

KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D