TANGO: Transparent heterogeneous hardware Architecture deployment for eNergy Gain in Operation

The paper is concerned with the issue of how software systems actually use Heterogeneous Parallel Architectures (HPAs), with the goal of optimizing power consumption on these resources. It argues the need for novel methods and tools to support software developers aiming to optimise power consumption resulting from designing, developing, deploying and running software on HPAs, while maintaining other quality aspects of software to adequate and agreed levels. To do so, a reference architecture to support energy efficiency at application construction, deployment, and operation is discussed, as well as its implementation and evaluation plans.Comment: Part of the Program Transformation for Programmability in Heterogeneous Architectures (PROHA) workshop, Barcelona, Spain, 12th March 2016, 7 pages, LaTeX, 3 PNG figure

A Dual Digital Signal Processor VME Board For Instrumentation And Control Applications

A Dual Digital Signal Processing VME Board was developed for the Continuous Electron Beam Accelerator Facility (CEBAF) Beam Current Monitor (BCM) system at Jefferson Lab. It is a versatile general-purpose digital signal processing board using an open architecture, which allows for adaptation to various applications. The base design uses two independent Texas Instrument (TI) TMS320C6711, which are 900 MFLOPS floating-point digital signal processors (DSP). Applications that require a fixed point DSP can be implemented by replacing the baseline DSP with the pin-for-pin compatible TMS320C6211. The design can be manufactured with a reduced chip set without redesigning the printed circuit board. For example it can be implemented as a single-channel DSP with no analog I/O.Comment: 3 PDF page

Neuro-inspired system for real-time vision sensor tilt correction

Neuromorphic engineering tries to mimic biological information processing. Address-Event-Representation (AER) is an asynchronous protocol for transferring the information of spiking neuro-inspired systems. Currently AER systems are able sense visual and auditory stimulus, to process information, to learn, to control robots, etc. In this paper we present an AER based layer able to correct in real time the tilt of an AER vision sensor, using a high speed algorithmic mapping layer. A codesign platform (the AER-Robot platform), with a Xilinx Spartan 3 FPGA and an 8051 USB microcontroller, has been used to implement the system. Testing it with the help of the USBAERmini2 board and the jAER software.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-02Ministerio de Ciencia e Innovación TEC2009-10639-C04-0

Development and testing of the Rho Sigma Incorporated microprocessor control subsystem

Product development and performance tests of three programmable microprocessor controllers for use with solar heating and cooling systems are presented. The products were developed to be marketable for public use

System for Anomaly and Failure Detection (SAFD) system development

This task specified developing the hardware and software necessary to implement the System for Anomaly and Failure Detection (SAFD) algorithm, developed under Technology Test Bed (TTB) Task 21, on the TTB engine stand. This effort involved building two units; one unit to be installed in the Block II Space Shuttle Main Engine (SSME) Hardware Simulation Lab (HSL) at Marshall Space Flight Center (MSFC), and one unit to be installed at the TTB engine stand. Rocketdyne personnel from the HSL performed the task. The SAFD algorithm was developed as an improvement over the current redline system used in the Space Shuttle Main Engine Controller (SSMEC). Simulation tests and execution against previous hot fire tests demonstrated that the SAFD algorithm can detect engine failure as much as tens of seconds before the redline system recognized the failure. Although the current algorithm only operates during steady state conditions (engine not throttling), work is underway to expand the algorithm to work during transient condition

Development of a character, line and point display system

A compact graphics terminal for use as the input to a computerized medical records system is described. The principal mode of communication between the terminal and the records system is by checklists and menu selection. However, the terminal accepts short, handwritten messages as well as conventional alphanumeric input. The terminal consists of an electronic tablet, a display, a microcomputer controller, a character generator, and a refresh memory for the display. An Intel SBC 80/10 microcomputer controls the flow of information and a 16 kilobyte memory stores the point-by-point array of information to be displayed. A specially designed interface continuously generates the raster display without the intervention of the microcomputer

Data acquisition system for the MuLan muon lifetime experiment

We describe the data acquisition system for the MuLan muon lifetime experiment at Paul Scherrer Institute. The system was designed to record muon decays at rates up to 1 MHz and acquire data at rates up to 60 MB/sec. The system employed a parallel network of dual-processor machines and repeating acquisition cycles of deadtime-free time segments in order to reach the design goals. The system incorporated a versatile scheme for control and diagnostics and a custom web interface for monitoring experimental conditions.Comment: 19 pages, 8 figures, submitted to Nuclear Instruments and Methods