75 research outputs found
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems
Neuromorphic chips embody computational principles operating in the nervous
system, into microelectronic devices. In this domain it is important to
identify computational primitives that theory and experiments suggest as
generic and reusable cognitive elements. One such element is provided by
attractor dynamics in recurrent networks. Point attractors are equilibrium
states of the dynamics (up to fluctuations), determined by the synaptic
structure of the network; a `basin' of attraction comprises all initial states
leading to a given attractor upon relaxation, hence making attractor dynamics
suitable to implement robust associative memory. The initial network state is
dictated by the stimulus, and relaxation to the attractor state implements the
retrieval of the corresponding memorized prototypical pattern. In a previous
work we demonstrated that a neuromorphic recurrent network of spiking neurons
and suitably chosen, fixed synapses supports attractor dynamics. Here we focus
on learning: activating on-chip synaptic plasticity and using a theory-driven
strategy for choosing network parameters, we show that autonomous learning,
following repeated presentation of simple visual stimuli, shapes a synaptic
connectivity supporting stimulus-selective attractors. Associative memory
develops on chip as the result of the coupled stimulus-driven neural activity
and ensuing synaptic dynamics, with no artificial separation between learning
and retrieval phases.Comment: submitted to Scientific Repor
Adaptive motor control and learning in a spiking neural network realised on a mixed-signal neuromorphic processor
Neuromorphic computing is a new paradigm for design of both the computing
hardware and algorithms inspired by biological neural networks. The event-based
nature and the inherent parallelism make neuromorphic computing a promising
paradigm for building efficient neural network based architectures for control
of fast and agile robots. In this paper, we present a spiking neural network
architecture that uses sensory feedback to control rotational velocity of a
robotic vehicle. When the velocity reaches the target value, the mapping from
the target velocity of the vehicle to the correct motor command, both
represented in the spiking neural network on the neuromorphic device, is
autonomously stored on the device using on-chip plastic synaptic weights. We
validate the controller using a wheel motor of a miniature mobile vehicle and
inertia measurement unit as the sensory feedback and demonstrate online
learning of a simple 'inverse model' in a two-layer spiking neural network on
the neuromorphic chip. The prototype neuromorphic device that features 256
spiking neurons allows us to realise a simple proof of concept architecture for
the purely neuromorphic motor control and learning. The architecture can be
easily scaled-up if a larger neuromorphic device is available.Comment: 6+1 pages, 4 figures, will appear in one of the Robotics conference
MorphIC: A 65-nm 738k-Synapse/mm Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning
Recent trends in the field of neural network accelerators investigate weight
quantization as a means to increase the resource- and power-efficiency of
hardware devices. As full on-chip weight storage is necessary to avoid the high
energy cost of off-chip memory accesses, memory reduction requirements for
weight storage pushed toward the use of binary weights, which were demonstrated
to have a limited accuracy reduction on many applications when
quantization-aware training techniques are used. In parallel, spiking neural
network (SNN) architectures are explored to further reduce power when
processing sparse event-based data streams, while on-chip spike-based online
learning appears as a key feature for applications constrained in power and
resources during the training phase. However, designing power- and
area-efficient spiking neural networks still requires the development of
specific techniques in order to leverage on-chip online learning on binary
weights without compromising the synapse density. In this work, we demonstrate
MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a
stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning
rule and a hierarchical routing fabric for large-scale chip interconnection.
The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF)
neurons and more than two million plastic synapses for an active silicon area
of 2.86mm in 65nm CMOS, achieving a high density of 738k synapses/mm.
MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy
tradeoff on the MNIST classification task compared to previously-proposed SNNs,
while having no penalty in the energy-accuracy tradeoff.Comment: This document is the paper as accepted for publication in the IEEE
Transactions on Biomedical Circuits and Systems journal (2019), the
fully-edited paper is available at
https://ieeexplore.ieee.org/document/876400
The importance of space and time in neuromorphic cognitive agents
Artificial neural networks and computational neuroscience models have made
tremendous progress, allowing computers to achieve impressive results in
artificial intelligence (AI) applications, such as image recognition, natural
language processing, or autonomous driving. Despite this remarkable progress,
biological neural systems consume orders of magnitude less energy than today's
artificial neural networks and are much more agile and adaptive. This
efficiency and adaptivity gap is partially explained by the computing substrate
of biological neural processing systems that is fundamentally different from
the way today's computers are built. Biological systems use in-memory computing
elements operating in a massively parallel way rather than time-multiplexed
computing units that are reused in a sequential fashion. Moreover, activity of
biological neurons follows continuous-time dynamics in real, physical time,
instead of operating on discrete temporal cycles abstracted away from
real-time. Here, we present neuromorphic processing devices that emulate the
biological style of processing by using parallel instances of mixed-signal
analog/digital circuits that operate in real time. We argue that this approach
brings significant advantages in efficiency of computation. We show examples of
embodied neuromorphic agents that use such devices to interact with the
environment and exhibit autonomous learning
Networks of spiking neurons and plastic synapses: implementation and control
The brain is an incredible system with a computational power that goes further beyond those
of our standard computer. It consists of a network of 1011 neurons connected by about 1014
synapses: a massive parallel architecture that suggests that brain performs computation
according to completely new strategies which we are far from understanding.
To study the nervous system a reasonable starting point is to model its basic units,
neurons and synapses, extract the key features, and try to put them together in simple
controllable networks. The research group I have been working in focuses its attention on
the network dynamics and chooses to model neurons and synapses at a functional level: in
this work I consider network of integrate-and-fire neurons connected through synapses that
are plastic and bistable. A synapses is said to be plastic when, according to some kind of
internal dynamics, it is able to change the “strength”, the efficacy, of the connection between
the pre- and post-synaptic neuron. The adjective bistable refers to the number of stable
states of efficacy that a synapse can have; we consider synapses with two stable states:
potentiated (high efficacy) or depressed (low efficacy). The considered synaptic model is
also endowed with a new stop-learning mechanism particularly relevant when dealing with
highly correlated patterns.
The ability of this kind of systems of reproducing in simulation behaviors observed in
biological networks, give sense to an attempt of implementing in hardware the studied
network. This thesis situates at this point: the goal of this work is to design, control and
test hybrid analog-digital, biologically inspired, hardware systems that behave in agreement
with the theoretical and simulations predictions. This class of devices typically goes under
the name of neuromorphic VLSI (Very-Large-Scale Integration). Neuromorphic engineering
was born from the idea of designing bio-mimetic devices and represents a useful research
strategy that contributes to inspire new models, stimulates the theoretical research and that
proposes an effective way of implementing stand-alone power-efficient devices.
In this work I present two chips, a prototype and a larger device, that are a step towards
endowing VLSI, neuromorphic systems with autonomous learning capabilities adequate for
not too simple statistics of the stimuli to be learnt. The main novel features of these
chips are the implemented type of synaptic plasticity and the configurability of the synaptic
connectivity. The reported experimental results demonstrate that the circuits behave in
agreement with theoretical predictions and the advantages of the stop-learning synaptic
plasticity when highly correlated patterns have to be learnt. The high degree of flexibility
of these chips in the definition of the synaptic connectivity is relevant in the perspective of
using such devices as building blocks of parallel, distributed multi-chip architectures that
will allow to scale up the network dimensions to systems with interesting computational
abilities capable to interact with real-world stimuli
Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems
Chicca E, Stefanini F, Bartolozzi C, Indiveri G. Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems. In: Proceedings of the IEEE. Proceedings of the IEEE. Vol 102. Piscataway, NJ: IEEE; 2014: 1367-1388.Several analog and digital brain-inspired electronic systems have been recently proposed as dedicated solutions for fast simulations of spiking neural networks. While these architectures are useful for exploring the computational properties of large-scale models of the nervous system, the challenge of building low-power compact physical artifacts that can behave intelligently in the real world and exhibit cognitive abilities still remains open. In this paper, we propose a set of neuromorphic engineering solutions to address this challenge. In particular, we review neuromorphic circuits for emulating neural and synaptic dynamics in real time and discuss the role of biophysically realistic temporal dynamics in hardware neural processing architectures; we review the challenges of realizing spike-based plasticity mechanisms in real physical systems and present examples of analog electronic circuits that implement them; we describe the computational properties of recurrent neural networks and show how neuromorphic winner-take-all circuits can implement working-memory and decision-making mechanisms. We validate the neuromorphic approach proposed with experimental results obtained from our own circuits and systems, and argue how the circuits and networks presented in this work represent a useful set of components for efficiently and elegantly implementing neuromorphic cognition
Mixed signal VLSI circuit implementation of the cortical microcircuit models
This thesis proposes a novel set of generic and compact biologically plausible VLSI (Very Large Scale Integration) neural circuits, suitable for implementing a parallel VLSI network that closely resembles the function of a small-scale neocortical network. The proposed circuits include a cortical neuron, two different long-term plastic synapses and four different short-term plastic synapses. These circuits operate in accelerated-time, where the time scale of neural responses is approximately three to four orders of magnitude faster than the biological-time scale of the neuronal activities, providing higher computational throughput in computing neural dynamics. Further, a novel biological-time cortical neuron circuit with similar dynamics as of the accelerated-time neuron is proposed to demonstrate the feasibility of migrating accelerated-time circuits into biological-time circuits. The fabricated accelerated-time VLSI neuron circuit is capable of replicating distinct firing patterns such as regular spiking, fast spiking, chattering and intrinsic bursting, by tuning two external voltages. It reproduces biologically plausible action potentials. This neuron circuit is compact and enables implementation of many neurons in a single silicon chip. The circuit consumes extremely low energy per spike (8pJ). Incorporating this neuron circuit in a neural network facilitates diverse non-linear neuron responses, which is an important aspect in neural processing. Two of the proposed long term plastic synapse circuits include spike-time dependent plasticity (STDP) synapse, and dopamine modulated STDP synapse. The short-term plastic synapses include excitatory depressing, inhibitory facilitating, inhibitory depressing, and excitatory facilitating synapses. Many neural parameters of short- and long- term synapses can be modified independently using externally controlled tuning voltages to obtain distinct synaptic properties. Having diverse synaptic dynamics in a network facilitates richer network behaviours such as learning, memory, stability and dynamic gain control, inherent in a biological neural network. To prove the concept in VLSI, different combinations of these accelerated-time neural circuits are fabricated in three integrated circuits (ICs) using a standard 0.35 µm CMOS technology. Using first two ICs, functions of cortical neuron and STDP synapses have been experimentally verified. The third IC, the Cortical Neural Layer (CNL) Chip is designed and fabricated to facilitate cortical network emulations. This IC implements neural circuits with a similar composition to the cortical layer of the neocortex. The CNL chip comprises 120 cortical neurons and 7 560 synapses. Many of these CNL chips can be combined together to form a six-layered VLSI neocortical network to validate the network dynamics and to perform neural processing of small-scale cortical networks. The proposed neuromorphic systems can be used as a simulation acceleration platform to explore the processing principles of biological brains and also move towards realising low power, real-time intelligent computing devices and control systems.EThOS - Electronic Theses Online ServiceGBUnited Kingdo
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