Investigation of decoupling capacitor connection methods using PEEC and study of alien crosstalk from a BroadR-Reach® protocol based system

Power Distribution Network (PDN) for Printed Circuit Board (PCB) design requires proper power integrity analysis. In order to deliver a low-ripple DC voltage from a Voltage Regulator Module (VRM) to an Integrated Circuit (IC), a certain target input impedance should be achieved. Developing simple physics-based equivalent circuit models are essential for understanding how a system works and making crucial design decisions. In this work, the input impedance of a decoupling capacitor due to traces, pads and via discontinuities are investigated using the Physics-based Model Size Reduction (PMSR) method. Various decoupling capacitor connection methods are compared and design guidelines are provided for reducing the equivalent inductance to meet target impedance requirements. It is shown that a shared pad having 179 pH equivalent Labove loop inductance is a better design choice as compared to a doublet or shared via design with 218 pH and 406 pH Labove loop inductance respectively. The second part of this thesis relates to BroadR-Reach® technology, a point-to-point Ethernet Physical Layer (PHY) standard, which is used in automotive applications. This technology allows full-duplex communication between two devices over a single, Unshielded Twisted wire Pair (UTP) cable. Here, alien crosstalk in a 6 UTP bundle is investigated for meeting electromagnetic compatibility requirements. The performance of Alien Near-End and Far-End Crosstalk of two different UTPs with and without an inline Circular Plastic Connector (CPC) are compared to standard limits. An inline connector in the middle of a 15 m 6 UTP cable bundle, with a 25 cm untwisted region fails the PSANEXT standard limit by 4 dB at 100 MHz, while the same bundle without the connector passes the standard by a margin of 8 dB at 100 MHz --Abstract, page iii

Performance and power optimization in VLSI physical design

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay

Optimal Positions of Twists in Global On-Chip Differential Interconnects

Abstract—Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect-pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect-pair and only two twists in every odd interconnect-pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10 mm long bus in 0.13 μm CMOS show that only one twist at 50% of the even interconnect-pairs, two twists at 30% and 70% of the odd interconnect-pairs and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstalk

Superconducting electromagnetic launch system for civil aircraft

This paper considers the feasibility of different superconducting technologies for electromagnetic launch (EML) to assist civil aircraft take-off. EML has the potential of reducing the required runway length by increasing aircraft acceleration. Expensive airport extensions to face constant air traffic growth could be avoided by allowing large aircraft to operate from short runways at small airports. The new system positively affects total aircraft noise and exhaust emissions near airports and improves overall aircraft efficiency through reducing engine design constraints. Superconducting Linear Synchronous Motors (SCLSMs) can be exploited to deliver the required take-off thrust with electromagnetic performance that cannot be easily achieved by conventional electrical machines. The sizing procedure of a SCLSM able to launch A320 in weight is presented. Electromagnetic and thermal aspects of the machine are taken into account including the modelling of ac losses in superconductors and thermal insulation. The metallic high temperature superconductor (HTS) magnesium diboride (MgB2) is used and operated at 20 K, the boiling temperature of liquid hydrogen. With modern manufacturing technology, multifilament MgB2 wires appear to be the most cost-effective solution for this application. Finally the impact of the cryocooler efficiency on the machine performance is evaluated

Inductance modeling for onchip interconnects

Abstract. As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization

High-Density Digital Links: Optimization of Signal Integrity and Noise Performance of the High-Density Digital Links of the ATLAS-TRT Readout System

The Transition Radiation Tracker (TRT) is a sub detector of the particle detector ATLAS (A Toroidal LHC ApparatuS). About 420,000 detecting elements are distributed over 22 m3. They produce each second approximately 20 Tbit of data which has to be transferred from the front-end electronics inside the detector to the back-end electronics outside the detector for further processing. The task of this thesis is to guarantee the integrity of the signals and the electromagnetic compatibility inside the TRT as well as to the aggressive surroundings. The electromagnetic environment of particle detectors in high-energy physics adds special constraints to the high data rates and the high complexity: high sensibility of the detecting elements and their pre amplifiers, confined space, limited material budget, a radioactive environment, and high static magnetic fields. Thus many industrial standard measures have to be abandoned. Special design is essential to compensate this disadvantage