Magnetic Matrix Memory System-Patent

Magnetic matrix memory system for nondestructive reading of information contained in matri

Binary magnetic memory device Patent

Nondestructive interrogating and state changing circuit for binary magnetic storage element

What constitutes a nanoswitch? A Perspective

Progress in the last two decades has effectively integrated spintronics and nanomagnetics into a single field, creating a new class of spin-based devices that are now being used both to Read (R) information from magnets and to Write (W) information onto magnets. Many other new phenomena are being investigated for nano-electronic memory as described in Part II of this book. It seems natural to ask whether these advances in memory devices could also translate into a new class of logic devices. What makes logic devices different from memory is the need for one device to drive another and this calls for gain, directionality and input-output isolation as exemplified by the transistor. With this in mind we will try to present our perspective on how W and R devices in general, spintronic or otherwise, could be integrated into transistor-like switches that can be interconnected to build complex circuits without external amplifiers or clocks. We will argue that the most common switch used to implement digital logic based on complementary metal oxide semiconductor (CMOS) transistors can be viewed as an integrated W-R unit having an input-output asymmetry that give it gain and directionality. Such a viewpoint is not intended to provide any insight into the operation of CMOS switches, but rather as an aid to understanding how W and R units based on spins and magnets can be combined to build transistor-like switches. Next we will discuss the standard W and R units used for magnetic memory devices and present one way to integrate them into a single unit with the input electrically isolated from the output. But we argue that this integrated W-R unit would not provide the key property of gain. We will then show that the recently discovered giant spin Hall effect could be used to construct a W-R unit with gain and suggest other possibilities for spin switches with gain.Comment: 27 pages. To appear in Emerging Nanoelectronic Devices, Editors: An Chen, James Hutchby, Victor Zhirnov and George Bourianoff, John Wiley & Sons (to be published

Self assembled three-dimensional nonvolatile memories

A promising strategy for for the realisation of three-dimensional memories could be the self assembly of articial sub-micron elements (smarticles). Such elements can be realised by combining edge-lithography techniques and anisotropic etching. The first experiments into this direction are encouraging

Engineering study for a mass memory system for advanced spacecrafts Final report, 1 Dec. 1969 - 1 Jul. 1970

Mass memory system for advanced spacecraf

A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems

In this paper, we present a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STTRAM) that can dynamically adapt the set capacity and associativity to use efficiently the full potential of MLC STTRAM. We exploit the asymmetric nature of the MLC storage scheme to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly, while the other is write-friendly. Furthermore, we propose to opportunistically deactivate ways in underutilized sets to convert MLC to Single-Level Cell (SLC) mode, which features overall better performance and lifetime. Our ultimate goal is to build a cache architecture that combines the capacity advantages of MLC and performance/energy advantages of SLC. Our experiments show an improvement of 43% in total numbers of conflict misses, 27% in memory access latency, 12% in system performance, and 26% in LLC access energy, with a slight degradation in cache lifetime (about 7%) compared to an SLC cache