Hardware support for memory protection in sensor nodes

With reference to the typical hardware configuration of a sensor node, we present the architecture of a memory protection unit (MPU) designed as a low-complexity addition to the microcontroller. The MPU is aimed at supporting memory protection and the privileged execution mode. It is connected to the system buses, and is seen by the processor as a memory-mapped input/output device. The contents of the internal MPU registers specify the composition of the protection contexts of the running program in terms of access rights for the memory pages. The MPU generates a hardware interrupt to the processor when it detects a protection violation. The proposed MPU architecture is evaluated from a number of salient viewpoints, which include the distribution, review and revocation of access permissions, and the support for important memory protection paradigms, including hierarchical contexts and protection rings

Memory protection in embedded systems

With reference to an embedded system featuring no support for memory management, we present a model of a protection system based on passwords. At the hardware level, our model takes advantage of a memory protection unit (MPU) interposed between the processor and the complex of the main memory and the input-output devices. The MPU supports both concepts of a protection context and a protection domain. A protection context is a set of access rights for the memory pages; a protection domain is a set of one or more protection contexts. Passwords are associated with protection domains. A process that holds a given password can take advantage of this password to activate the corresponding domain. A small set of protection primitives makes it possible to modify the composition of the domains in a strictly controlled fashion. The proposed protection model is evaluated from a number of important viewpoints, which include password distribution, review and revocation, the memory requirements for storage of the information concerning protection, and the time necessary for password validation

Distributed storage protection in wireless sensor networks

With reference to a distributed architecture consisting of sensor nodes connected in a wireless network, we present a model of a protection system based on segments and applications. An application is the result of the joint activities of a set of cooperating nodes. A given node can access a segment stored in the primary memory of a different node only by presenting a gate for that segment. A gate is a form of pointer protected cryptographically, which references a segment and specifies a set of access rights for this segment. Gates can be freely transmitted between nodes, thereby granting the corresponding access permissions. Two special node functionalities are considered, segment servers and application servers. Segment servers are used for inter-application communication and information gathering. An application server is used in each application to support key management and rekeying. The rekey mechanism takes advantage of key naming to cope with losses of rekey messages. The total memory requirements for key and gate storage result to be a negligible fraction of the overall memory resources of the generic network node

A System For Coarse Grained Memory Protection In Tiny Embedded Processors ABSTRACT

Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides memory protection in tiny embedded processors. 1. Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected memory region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of memory protection with minimal impact on performance and a modest increase in the area of the microcontroller

Leveraging Processor Features for System Security

Errors in hardware and software lead to vulnerabilities that can be exploited by attackers. Proposed exploit mitigation techniques can be broadly categorized into two: software-only techniques and techniques that propose specialized hardware extensions. Software-only techniques can be implemented on existing hardware, but typically suffer from impractically high overheads. On the other hand, specialized hardware extensions, while improving performance, in practice require a long time to be incorporated into production hardware. In this dissertation, we propose adapting existing processor features to provide novel and low-overhead security solutions. In the first part of the dissertation, we show how modern hardware features can be used to provide efficient memory safety. One component of memory safety that has become important in recent years is temporal memory safety. Temporal memory safety techniques are used to detect memory errors such as use-after-free errors. This dissertation proposes a temporal memory safety technique that takes advantage of pointer authentication hardware to significantly reduce the memory and runtime overhead of traditional temporal safety techniques. Providing complete memory safety on resource constrained devices is expensive, therefore we propose software-based fault isolation (sandboxing) as an efficient alternative to constrain attackers’ access to code and data in embedded systems. We show how we can use the memory protection unit (MPU) hardware available in many embedded devices along with a small trusted runtime to build a low-overhead sandboxing mechanism. In the second part of the dissertation, we show how hardware performance counters in modern processors can be used to detect rowhammer attacks. Our technique detects rowhammer attacks by monitoring for high locality memory accesses out of the last-level cache using hardware performance counters. The technique accurately detects rowhammer attacks with a low performance overhead and without requiring hardware modifications.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/149852/1/zaweke_1.pd