Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital component in today's SoCs. Diverse technologies such as electrical, wireless, optical, and hybrid are available for on-chip communication with different architectures supporting them. Security of the on-chip communication is crucial because exploiting any vulnerability would be a goldmine for an attacker. In this survey, we provide a comprehensive review of threat models, attacks, and countermeasures over diverse on-chip communication technologies as well as sophisticated architectures.Comment: 41 pages, 24 figures, 4 table

A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Large-Scale Optical Neural Networks based on Photoelectric Multiplication

Recent success in deep neural networks has generated strong interest in hardware accelerators to improve speed and energy consumption. This paper presents a new type of photonic accelerator based on coherent detection that is scalable to large ($N \gtrsim 10^6$) networks and can be operated at high (GHz) speeds and very low (sub-aJ) energies per multiply-and-accumulate (MAC), using the massive spatial multiplexing enabled by standard free-space optical components. In contrast to previous approaches, both weights and inputs are optically encoded so that the network can be reprogrammed and trained on the fly. Simulations of the network using models for digit- and image-classification reveal a "standard quantum limit" for optical neural networks, set by photodetector shot noise. This bound, which can be as low as 50 zJ/MAC, suggests performance below the thermodynamic (Landauer) limit for digital irreversible computation is theoretically possible in this device. The proposed accelerator can implement both fully-connected and convolutional networks. We also present a scheme for back-propagation and training that can be performed in the same hardware. This architecture will enable a new class of ultra-low-energy processors for deep learning.Comment: Text: 10 pages, 5 figures, 1 table. Supplementary: 8 pages, 5, figures, 2 table

In-band label extractor based on Cascaded Si ring resonators enabling 160 Gb/s optical packet switching modules

Photonic integration of optical packet switching modules is crucial to compete with existing electronic switching fabrics in large data center networks. The approach of coding the forwarding packet information in an in-band label enables a spectral-efficient and scalable way of building low-latency large port count modular optical packet switching architecture. We demonstrate the error-free operation of the four in-band label extraction from 160 Gb/s optical data packets based on photonic integrated silicon-on- insulator ring resonators. Four low-loss cascaded ring resonators using the quasi-TM mode are used as narrowband filters to ensure the detection of four optical labels as well as the error-free forwarding of the payload at limited power penalty. Due to the low-loss and less-confined optical quasi-TM mode the resonators can be very narrowband and have low insertion loss. The effect of the bandwidth of the four ring resonators on the quality of the payload is investigated. We show that using four rings with 3dB bandwidth of 21 pm and only an insertion loss of 3 dB, the distortion on the payload is limited (< 1.5 dB power penalty), even when the resonances are placed very close to the packet's central wavelength. We also investigate the optical power requirements for error-free detection of the label as function of their spectral position relative to the center of the payload. The successful in-band positioning of the labels makes this component very scalable in amount of labels

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Expanded-beam backside coupling interface for alignment-tolerant packaging of silicon photonics

We demonstrate an alignment-tolerant backside coupling interface in the O-band for silicon photonics by generating an optimized through-substrate (downward) directionality beam from a TE-mode grating coupler and hybrid integrating the chip with backside silicon microlenses to achieve expanded beam collimation. The key advantage of using such an expanded beam interface is an increased coupling tolerance to lateral and longitudinal misalignment. A 34 mu m beam diameter was achieved over a combined substrate thickness of 630 mu m which was then coupled to a thermally expanded core single-mode fiber to investigate the tolerances. A 1-dB fiber-to-microlens lateral alignment tolerance of 14 mu m and an angular alignment tolerance of 1 degrees was measured at a wavelength of 1310 nm. In addition, a large +/- 2.5 mu m 1-dB backside alignment accuracy was measured for the placement of microlens with respect to the grating. The radius of curvature of Si microlens to achieve a collimated beam was 480 mu m, and a 1-dB longitudinal alignment tolerance of 700 mu m was measured for coupling to a single-mode expanded core fiber. The relaxation in alignment tolerances make the demonstrated coupling interface suitable for chip-to-package or chip-to-board couplin