Battery-sourced switched-inductor multiple-output CMOS power-supply systems

Wireless microsystems add intelligence to larger systems by sensing, processing and transmitting information which can ultimately save energy and resources. Each function has their own power profile and supply level to maximize performance and save energy since they are powered by a small battery. Also, due to its small size, the battery has limited energy and therefore the power-supply system cannot consume much power. Switched-inductor converters are efficient across wide operating conditions but one fundamental challenge is integration because miniaturized dc-dc converters cannot afford to accommodate more than one off-chip power inductor. The objective of this research is to explore, develop, analyze, prototype, test, and evaluate how one switched inductor can derive power from a small battery to supply, regulate, and respond to several independent outputs reliably and accurately. Managing and stabilizing the feedback loops that supply several outputs at different voltages under diverse and dynamic loading conditions with one CMOS chip and one inductor is also challenging. Plus, since a single inductor cannot supply all outputs at once, steady-state ripples and load dumps produce cross-regulation effects that are difficult to manage and suppress. Additionally, as the battery depletes the power-supply system must be able to regulate both buck and boost voltages. The presented system can efficiently generate buck and boost voltages with the fastest response time while having a low silicon area consumption per output in a low-cost technology which can reduce the overall size and cost of the system.Ph.D

Nano-Power Integrated Circuits for Energy Harvesting

The energy harvesting research field has grown considerably in the last decade due to increasing interests in energy autonomous sensing systems, which require smart and efficient interfaces for extracting power from energy source and power management (PM) circuits. This thesis investigates the design trade-offs for minimizing the intrinsic power of PM circuits, in order to allow operation with very weak energy sources. For validation purposes, three different integrated power converter and PM circuits for energy harvesting applications are presented. They have been designed for nano-power operations and single-source converters can operate with input power lower than 1 μW. The first IC is a buck-boost converter for piezoelectric transducers (PZ) implementing Synchronous Electrical Charge Extraction (SECE), a non-linear energy extraction technique. Moreover, Residual Charge Inversion technique is exploited for extracting energy from PZ with weak and irregular excitations (i.e. lower voltage), and the implemented PM policy, named Two-Way Energy Storage, considerably reduces the start-up time of the converter, improving the overall conversion efficiency. The second proposed IC is a general-purpose buck-boost converter for low-voltage DC energy sources, up to 2.5 V. An ultra-low-power MPPT circuit has been designed in order to track variations of source power. Furthermore, a capacitive boost circuit has been included, allowing the converter start-up from a source voltage VDC0 = 223 mV. A nano-power programmable linear regulator is also included in order to provide a stable voltage to the load. The third IC implements an heterogeneous multisource buck-boost converter. It provides up to 9 independent input channels, of which 5 are specific for PZ (with SECE) and 4 for DC energy sources with MPPT. The inductor is shared among channels and an arbiter, designed with asynchronous logic to reduce the energy consumption, avoids simultaneous access to the buck-boost core, with a dynamic schedule based on source priority

FPGA Operating System for Hard Real Time Applications

In mechatronics, as in many others fields, one of the main aspect is the prototyping. Since the mechatronics covers a lot of complex applications, the availability of a common digital platform to use in all of them is a valid help in the prototyping phase of the project. FPGAs are often used as software acceleration in reconfigurable computers (RC), in which the operating system is a standard off-the-shelf real time operating system such as Linux and VxWorks. The object of the first part of the work is to develop a hardware operating system for mechatronic applications, which means that the FPGA device does not host a soft core processor, able to execute one only operation at a time, but it executes many concurrent hard real time functions allowing the user to develop his own application code taking advantage of the main features of the device: concurrency, flexibility and determinism. The second part of the thesis is related to the project of an electronic module that integrates logic and power devices to drive piezoelectric stack actuators and demonstrate experimentally the results in terms of control of piezoelectric stack tip displacement on atest bench. The electronic module controls up to four piezoelectric stack actuators and guarantees that the correct tip displacement is reached starting from a desired profile. The various opening/closing phases of the actuators are tuned in terms of slew rate, timings and values to reach during all the controlled phase. The control parameters are passed to the control unit by means of a host human machine interface or by an external electronic control unit that acts as a supervisor. This part will illustrate all the passages of the design starting from the constitutive equations of the piezoelectric material up to the final architecture of the control law and implementation passing through: • creation of a FEM model of the piezoelectric stack; • construction of the modal residues model; • FEM model validation; • identification of the electrical equivalent circuit of the piezoelectric stack; • design of the power driver circuit; • design of the control loops; A complete model validation is then performed and experimental results are presente

Design of High Power Converter with SiC MOSFETs

Tato diplomová práce se zabývá návrhem výkonového měniče založeného na topologii typu synchronní buck. Měnič je zkonstruován s využitím MOSFET tranzistorů na bázi silikon karbidu. Tato práce se věnuje analýze měniče s cílem navrhnout a realizovat řídící jednotku umožňující jak zpětnovazební regulaci měniče, tak řízení v otevřené smyčce. Za tímto účelem je odvozen analytický model měniče coby dynamického systému, který je použit pro návrh a simulaci řízení. Kontrolní jednotka je implementována s využitím 32 bitového mikrořadiče založeného na architektuře ARM. V této práci je poskytnut popis a použití klíčových periférií mikrořadiče pro realizaci řízení. Na závěr jsou shrnuty výsledky měření dynamického chování výkonových tranzistorů při provozu měniče. Pozornost je především věnována měření proudu tekoucího jedním tranzistorem s využitím běžného rezistoru pro snímání proudu a kompenzaci frekvenční charakteristiky rezistoru.This master degree thesis is concerned with the design of high power converter. The converter is based on synchronous buck topology and is realized using silicon carbide MOSFET transistors. This work deals with an analysis of such type of converter to design and realize a control unit providing feedback control of the converter. Therefore, a dynamic model of the converter is derived using a conventional technique of averaged state space modeling. The derived model is used for controller design and closed-loop control simulation. The control unit is implemented using a 32-bit ARM-based microcontroller. Hence, an insight into the microcontroller key peripherals is provided as well as a brief overview of the firmware architecture. This work concludes by a brief investigation of switching waveforms of SiC MOSFETs acquired during the converter operation. Attention is called to a transistor current measurement with a low-cost current sensing resistor and its frequency characteristic compensation

Low Voltage Regulator Modules and Single Stage Front-end Converters

Evolution in microprocessor technology poses new challenges for supplying power to these devices. To meet demands for faster and more efficient data processing, modem microprocessors are being designed with lower voltage implementations. More devices will be packed on a single processor chip and the processors will operate at higher frequencies, exceeding 1GHz. New high-performance microprocessors may require from 40 to 80 watts of power for the CPU alone. Load current must be supplied with up to 30A/µs slew rate while keeping the output voltage within tight regulation and response time tolerances. Therefore, special power supplies and Voltage Regulator Modules (VRMs) are needed to provide lower voltage with higher current and fast response. In the part one (chapter 2,3,4) of this dissertation, several low-voltage high-current VRM technologies are proposed for future generation microprocessors and ICs. The developed VRMs with these new technologies have advantages over conventional ones in terms of efficiency, transient response and cost. In most cases, the VRMs draw currents from DC bus for which front-end converters are used as a DC source. As the use of AC/DC frond-end converters continues to increase, more distorted mains current is drawn from the line, resulting in lower power factor and high total harmonic distortion. As a branch of active Power factor correction (PFC) techniques, the single-stage technique receives particular attention because of its low cost implementation. Moreover, with continuously demands for even higher power density, switching mode power supply operating at high-frequency is required because at high switching frequency, the size and weight of circuit components can be remarkably reduced. To boost the switching frequency, the soft-switching technique was introduced to alleviate the switching losses. The part two (chapter 5,6) of the dissertation presents several topologies for this front-end application. The design considerations, simulation results and experimental verification are discussed

Quad- bus motor drive system for electrified vehicles based on a dual- output- single- inductor structure

Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/163903/1/elp2bf00838.pd

Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications

Heading towards the era of Internet-of-things (IoT) means both opportunity and challenge for the circuit-design community. In a system where billions of devices are equipped with the ability to sense, compute, communicate with each other and perform tasks in a coordinated manner, security and power management are among the most critical challenges. Physically unclonable function (PUF) emerges as an important security primitive in hardware-security applications; it provides an object-specific physical identifier hidden within the intrinsic device variations, which is hard to expose and reproduce by adversaries. Yet, designing a compact PUF robust to noise, temperature and voltage remains a challenge. This thesis presents a novel PUF design approach based on a pair of ultra-compact analog circuits whose output is proportional to absolute temperature. The proposed approach is demonstrated through two works: (1) an ultra-compact and robust PUF based on voltage-compensated proportional-to-absolute-temperature voltage generators that occupies 8.3× less area than the previous work with the similar robustness and twice the robustness of the previously most compact PUF design and (2) a technique to transform a 6T-SRAM array into a robust analog PUF with minimal overhead. In this work, similar circuit topology is used to transform a preexisting on-chip SRAM into a PUF, which further reduces the area in (1) with no robustness penalty. In this thesis, we also explore techniques for power management circuit design. Energy harvesting is an essential functionality in an IoT sensor node, where battery replacement is cost-prohibitive or impractical. Yet, existing energy-harvesting power management units (EH PMU) suffer from efficiency loss in the two-step voltage conversion: harvester-to-battery and battery-to-load. We propose an EH PMU architecture with hybrid energy storage, where a capacitor is introduced in addition to the battery to serve as an intermediate energy buffer to minimize the battery involvement in the system energy flow. Test-case measurements show as much as a 2.2× improvement in the end-to-end energy efficiency. In contrast, with the drastically reduced power consumption of IoT nodes that operates in the sub-threshold regime, adaptive dynamic voltage scaling (DVS) for supply-voltage margin removal, fully on-chip integration and high power conversion efficiency (PCE) are required in PMU designs. We present a PMU–load co-design based on a fully integrated switched-capacitor DC-DC converter (SC-DC) and hybrid error/replica-based regulation for a fully digital PMU control. The PMU is integrated with a neural spike processor (NSP) that achieves a record-low power consumption of 0.61 µW for 96 channels. A tunable replica circuit is added to assist the error regulation and prevent loss of regulation. With automatic energy-robustness co-optimization, the PMU can set the SC-DC’s optimal conversion ratio and switching frequency. The PMU achieves a PCE of 77.7% (72.2%) at VIN = 0.6 V (1 V) and at the NSP’s margin-free operating point

High power high frequency DC-DC converter topologies for use in off-line power supplies

The development of a DC-DC converter for use in a proposed range of one to ten kilowatt off-line power supplies is presented. The converter makes good use of established design practices and recent technical advances. The thesis begins with a review of traditional design practices, which are used in the design of a 3kW, 48V output DC-DC converter, as a bench-mark for evaluation of recent technical advances. Advances evaluated include new converter circuits, control techniques, components, and magnetic component designs. Converter circuits using zero voltage switching (ZVS) transitions offer significant advantages for this application. Of the published converters which have ZVS transitions the phase shift controlled full bridge converter is the most suitable, and assessments of variations on this circuit are presented. During the course of the research it was realised that the ZVS range of one leg of the phase shift controlled full bridge converter could be extended by altering the switching pattern, and this new switching pattern is proposed. A detailed analysis of phase shift controlled full bridge converter operation uncovers a number of operational findings which give a better and more complete understanding of converter operation than hitherto published. Converter design equations and guidelines are presented and the effects of the new improvement are investigated by an approximate analysis. Computer simulations using PSPICE2 are carried out to predict converter performance. A prototype converter design, construction details and test results are given. The results obtained compare well to the predicted performance and confirm the advantages of the new switching pattern

Integrated Voltage Regulators with Thin-Film Magnetic Power Inductors

Integration of alternative materials and devices with CMOS will expand functionality and improve performance of established applications in the era of diminishing returns from Moore's Law scaling. In particular, integration of thin-film magnetic materials will enable improvements in energy efficiency of digital computing applications by enabling integrated power conversion and management with on-chip power inductors. Integrated voltage reg- ulators will also enable fine-grained power management, by providing dynamic scaling of the supply voltage in concert with the clock frequency of synchronous logic to throttle power consumption at periods of low computational demand. Implementation of integrated power conversion requires high capacity energy storage devices. This is best achieved with integration of thin-film magnetic materials for high quality on-chip power inductors. This thesis describes a body of work conducted to develop integrated switch-mode voltage regulators with thin-film magnetic power inductors. Soft-magnetic materials and inductor topologies are selected and optimized, with intent to maximize efficiency and current density of the integrated regulators. Custom integrated circuits are designed and fabricated in 45nm-SOI to provide the control system and power-train necessary to drive the power inductors. A silicon interposer is designed and fabricated in collaboration with IBM Research to integrate custom power inductors by 2.5D chip stacking, enabling power conversion with current density greater than 10A/mm2. The concepts and designs developed from this work will enable significant improvements in performance-per-watt of future microprocessors