Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

A Low-Power Wireless Multichannel Microsystem for Reliable Neural Recording.

This thesis reports on the development of a reliable, single-chip, multichannel wireless biotelemetry microsystem intended for extracellular neural recording from awake, mobile, and small animal models. The inherently conflicting requirements of low power and reliability are addressed in the proposed microsystem at architectural and circuit levels. Through employing the preliminary microsystems in various in-vivo experiments, the system requirements for reliable neural recording are identified and addressed at architectural level through the analytical tool: signal path co-optimization. The 2.85mm×3.84mm, mixed-signal ASIC integrates a low-noise front-end, programmable digital controller, an RF modulator, and an RF power amplifier (PA) at the ISM band of 433MHz on a single-chip; and is fabricated using a 0.5µm double-poly triple-metal n-well standard CMOS process. The proposed microsystem, incorporating the ASIC, is a 9-channel (8-neural, 1-audio) user programmable reliable wireless neural telemetry microsystem with a weight of 2.2g (including two 1.5V batteries) and size of 2.2×1.1×0.5cm3. The electrical characteristics of this microsystem are extensively characterized via benchtop tests. The transmitter consumes 5mW and has a measured total input referred voltage noise of 4.74µVrms, 6.47µVrms, and 8.27µVrms at transmission distances of 3m, 10m, and 20m, respectively. The measured inter-channel crosstalk is less than 3.5% and battery life is about an hour. To compare the wireless neural telemetry systems, a figure of merit (FoM) is defined as the reciprocal of the power spent on broadcasting one channel over one meter distance. The proposed microsystem’s FoM is an order of magnitude larger compared to all other research and commercial systems. The proposed biotelemetry system has been successfully used in two in-vivo neural recording experiments: i) from a freely roaming South-American cockroach, and ii) from an awake and mobile rat.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91542/1/aborna_1.pd

Integrated temperature sensors in deep sub-micron CMOS technologies

textIntegrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.Electrical and Computer Engineerin

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Increasing number of energy-limited applications continue to drive the demand for designing systems with high energy efficiency. This tutorial covers the main building blocks of a system implementation including digital logic, embedded memories, and analog-to-digital converters and describes the challenges and solutions to designing these blocks for low-voltage operation

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Ultra-low Power Circuits for Internet of Things (IOT)

Miniaturized sensor nodes offer an unprecedented opportunity for the semiconductor industry which led to a rapid development of the application space: the Internet of Things (IoT). IoT is a global infrastructure that interconnects physical and virtual things which have the potential to dramatically improve people's daily lives. One of key aspect that makes IoT special is that the internet is expanding into places that has been ever reachable as device form factor continue to decreases. Extremely small sensors can be placed on plants, animals, humans, and geologic features, and connected to the Internet. Several challenges, however, exist that could possibly slow the development of IoT. In this thesis, several circuit techniques as well as system level optimizations to meet the challenging power/energy requirement for the IoT design space are described. First, a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems is presented. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. Second, an ultra-low power oscillator designed for wake-up timers in compact wireless sensors is presented. The proposed topology separates the continuous comparator from the oscillation path and activates it only for short period when it is required. As a result, both low power tracking and generation of precise wake-up signal is made possible. Third, an 8-bit sub-ranging SAR ADC for biomedical applications is discussed that takes an advantage of signal characteristics. ADC uses a moving window and stores the previous MSBs voltage value on a series capacitor to achieve energy saving compared to a conventional approach while maintaining its accuracy. Finally, an ultra-low power acoustic sensing and object recognition microsystem that uses frequency domain feature extraction and classification is presented. By introducing ultra-low 8-bit SAR-ADC with 50fF input capacitance, power consumption of the frontend amplifier has been reduced to single digit nW-level. Also, serialized discrete Fourier transform (DFT) feature extraction is proposed in a digital back-end, replacing a high-power/area-consuming conventional FFT.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137157/1/seojeong_1.pd

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e TecnologiaSignal amplification is required in almost every analog electronic system. However noise is also present, thus imposing limits to the overall circuit performance, e.g., on the sensitivity of the radio transceiver. This drawback has triggered a major research on the field, which has been producing several solutions to achieve amplification with minimum added noise. During the Fifties, an interesting out of mainstream path was followed which was based on variable reactance instead of resistance based amplifiers. The principle of these parametric circuits permits to achieve low noise amplifiers since the controlled variations of pure reactance elements is intrinsically noiseless. The amplification is based on a mixing effect which enables energy transfer from an AC pump source to other related signal frequencies. While the first implementations of these type of amplifiers were already available at that time, the discrete-time version only became visible more recently. This discrete-time version is a promising technique since it is well adapted to the mainstream nanoscale CMOS technology. The technique itself is based on the principle of changing the surface potential of the MOS device while maintaining the transistor gate in a floating state. In order words, the voltage amplification is achieved by changing the capacitance value while maintaining the total charge unchanged during an amplification phase. Since a parametric amplifier is not intrinsically dependent on the transconductance of the MOS transistor, it does not directly suffer from the intrinsic transconductance MOS gain issues verified in nanoscale MOS technologies. As a consequence, open-loop and opamp free structures can further emerge with this additional contribution. This thesis is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. The use of the latter is supported on the presentation of several circuits where the MOS Parametric Amplifier cell is well suited: small gain amplifier, comparator, discrete-time mixer and filter, and ADC. Relatively to the latter, a high speed time-interleaved pipeline ADC prototype is implemented in a,standard 130 nm CMOS digital technology from United Microelectronics Corporation (UMC). The ADC is fully based on parametric MOS amplification which means that one could achieve a compact and MOS-only implementation. Furthermore, any high speed opamp has not been used in the signal path, being all the amplification steps implemented with open-loop parametric MOS amplifiers. To the author’s knowledge, this is first reported pipeline ADC that extensively used the parametric amplification concept.Fundação para a Ciência e Tecnologia through the projects SPEED, LEADER and IMPAC