The Design of a single chip 8x8 ATM switch in 0.5 micrometers CMOS VLSI

This thesis illustrates the design of a single chip Asynchronous Transfer Mode (ATM) protocol switch using Very Large Scale Integration (VLSI). The ATM protocol is the data communications protocol used in the implementation of the Broadband Integrated Services Digital Network (B-ISDN), A number of switch architecture are first studied and a new architecture is developed based on optimizing performance and practicality of implementation in VLSI. A fully interconnected switch architecture is implemented by permanently connecting every input port to all the output ports. An output buffering scheme is used to handle cells that cannot be routed right away. This new architecture is caned the High Performance (HiPer) Switch Architecture. The performance of the architecture is simulated using a C++ model. Simulation results for a randomly distributed traffic pattern with a 90% probability of cells arriving in a time slot produces a Cell Loss Ratio of 1.Ox 10^-8 with output buffers that can hold 64 cells. The device is then modeled in VHDL to verify its functionality. Finally the layout of an 8x8 switch is produced using a 0.5 micrometer CMOS VLSI process and simulations of that circuit show that a peak throughput of 200 Mbps per output port can be achieve

Satellite Networks: Architectures, Applications, and Technologies

Since global satellite networks are moving to the forefront in enhancing the national and global information infrastructures due to communication satellites' unique networking characteristics, a workshop was organized to assess the progress made to date and chart the future. This workshop provided the forum to assess the current state-of-the-art, identify key issues, and highlight the emerging trends in the next-generation architectures, data protocol development, communication interoperability, and applications. Presentations on overview, state-of-the-art in research, development, deployment and applications and future trends on satellite networks are assembled

The 25 kW power module evolution study. Part 3: Conceptual designs for power module evolution. Volume 4: Design analyses

Topics covered include growth options evaluation, mass properties, attitude control and structural dynamics, contamination evaluation, berthing concepts, orbit reboost options and growth kit concepts. Systems support elements and space support equipment are reviewed with emphasis on power module operations and technology planning

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Aviation System Analysis Capability Executive Assistant Design

In this technical document, we describe the design developed for the Aviation System Analysis Capability (ASAC) Executive Assistant (EA) Proof of Concept (POC). We describe the genesis and role of the ASAC system, discuss the objectives of the ASAC system and provide an overview of components and models within the ASAC system, and describe the design process and the results of the ASAC EA POC system design. We also describe the evaluation process and results for applicable COTS software. The document has six chapters, a bibliography, three appendices and one attachment

Statistical model identification : dynamical processes and large-scale networks in systems biology

Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2014von Robert Johann Flassi

NASA Tech Briefs, June 1996

Topics: New Computer Hardware; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Manufacturing/Fabrication; Mathematics and Information Sciences;Books and Reports

Design and analysis of an ATM network traffic security device

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to [email protected], referencing the URI of the item.Includes bibliographical references: p. 77-79.Issued also on microfiche from Lange Micrographics.Not availabl