Dynamic reconfiguration technologies based on FPGA in software defined radio system

Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design

Development of a Multi-Standard Protocol Using Software Defined Radio for a Mobile Station Transceiver

In this thesis, the Software Defined Radio Digital Control System (SDR DCS) has been developed to perform a multi-standard protocol of the handset using the GSM and CDMA systems. The SDR DCS was designed for the SDR based band digital transceiver of the handset as a control and protocol software to control and handle the operation of the handset when roaming between different protocols; it could easily and quickly let the handset reconfigure with the future protocol; it configured the handset with either of the GSM or CDMA protocol software, and scheduled for reconfiguration of the handset with the second protocol in sequence. The SDR DCS controls the download of the specific air interface environment. In order to implement the whole design in software, the design had to go through three stages. The first stage was to do all the design steps in the software using generic computing resources such as Hardware Description Language (HDL), with the top-level design for each protocol. The second stage was to define a logic circuit to perform the signal processing for each protocol; this step was applied after the simulation and synthesis, and eventually programming that circuit into the FPGA board. The third stage was to use the FPGA to implement the functions required for each protocol which constitutes the multi-standard protocol. The VHDL files were created for each element of the GSM and CDMA protocols. The GSM related system was developed with encoders and decoders linked to the channel model. The CDMA related system was designed with a transmitter to encode the user’s data into wide bandwidth using a reverse link channel and a synchronized receiver to receive the signal from the forward link channel and decode the wide bandwidth to recover the base band user’s data. The Synopsys™ software package was used for the design, synthesis and simulation of the SDR base band platform. The simulation tools used include the Model Sim and System Studio. Meanwhile, the Xilinx ISE 9.2i was used as the synthesis tool. The results of the simulated and synthesized top-level design files were downloaded into the Xilinx XSA-3S1000 FPGA board. The waveforms for the GSM and CDMA outputs approximately matched the ones seen in the oscilloscope for the FPGA output pin. This proved that the SDR DCS had successfully implemented its task, according to the objectives of the design

Multi-standard programmable baseband modulator for next generation wireless communication

Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the software to be downloaded and also limits the hardware reconfiguration time. The present paper is based on the design and development of a programmable baseband modulator that perform the QPSK modulation schemes and as well as its other three commonly used variants to satisfy the requirement of several established 2G and 3G wireless communication standards. The proposed design has been shown to be capable of operating at a maximum data rate of 77 Mbps on Xilinx Virtex 2-Pro University field programmable gate array (FPGA) board. The pulse shaping root raised cosine (RRC) filter has been implemented using distributed arithmetic (DA) technique in the present work in order to reduce the computational complexity, and to achieve appropriate power reduction and enhanced throughput. The designed multiplier-less programmable 32-tap FIR-based RRC filter has been found to withstand a peak inter-symbol interference (ISI) distortion of -41 dB

Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed