Room-Temperature Sputtered SnO2 as Robust Electron Transport Layer for Air-Stable and Efficient Perovskite Solar Cells on Rigid and Flexible Substrates.

Extraordinary photovoltaic performance and intriguing optoelectronic properties of perovskite solar cells (PSCs) have aroused enormous interest from both academic research and photovoltaic (PV) industry. In order to bring PSC technology from laboratory to market, material stability, device flexibility, and scalability are important issues to address for vast production. Nevertheless, PSCs are still primarily prepared by solution methods which limit film scalability, while high-temperature processing of metal oxide electron transport layer (ETL) makes PSCs costly and incompatible with flexible substrates. Here, we demonstrate rarely-reported room-temperature radio frequency (RF) sputtered SnO2 as a promising ETL with suitable band structure, high transmittance, and excellent stability to replace its solution-processed counterpart. Power conversion efficiencies (PCEs) of 12.82% and 5.88% have been achieved on rigid glass substrate and flexible PEN substrate respectively. The former device retained 93% of its initial PCE after 192-hour exposure in dry air while the latter device maintained over 90% of its initial PCE after 100 consecutive bending cycles. The result is a solid stepping stone toward future PSC all-vapor-deposition fabrication which is being widely used in the PV industry now

Development of a strontium optical lattice clock for the SOC mission on the ISS

The ESA mission "Space Optical Clock" project aims at operating an optical lattice clock on the ISS in approximately 2023. The scientific goals of the mission are to perform tests of fundamental physics, to enable space-assisted relativistic geodesy and to intercompare optical clocks on the ground using microwave and optical links. The performance goal of the space clock is less than $1 \times 10^{-17}$ uncertainty and $1 \times 10^{-15} {\tau}^{-1/2}$ instability. Within an EU-FP7-funded project, a strontium optical lattice clock demonstrator has been developed. Goal performances are instability below $1 \times 10^{-15} {\tau}^{-1/2}$ and fractional inaccuracy $5 \times 10^{-17}$. For the design of the clock, techniques and approaches suitable for later space application are used, such as modular design, diode lasers, low power consumption subunits, and compact dimensions. The Sr clock apparatus is fully operational, and the clock transition in $^{88}$Sr was observed with linewidth as small as 9 Hz.Comment: 12 pages, 8 figures, SPIE Photonics Europe 201

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a System-on-Chip based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with secured remote recognition in 5.74pJ/op; and seizure detection with encrypted data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE Transactions on Circuits and Systems - I: Regular Paper

Dynamic Power Management for Neuromorphic Many-Core Systems

This work presents a dynamic power management architecture for neuromorphic many core systems such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) technique is presented which allows the processing elements (PE) to change their supply voltage and clock frequency individually and autonomously within less than 100 ns. This is employed by the neuromorphic simulation software flow, which defines the performance level (PL) of the PE based on the actual workload within each simulation cycle. A test chip in 28 nm SLP CMOS technology has been implemented. It includes 4 PEs which can be scaled from 0.7 V to 1.0 V with frequencies from 125 MHz to 500 MHz at three distinct PLs. By measurement of three neuromorphic benchmarks it is shown that the total PE power consumption can be reduced by 75%, with 80% baseline power reduction and a 50% reduction of energy per neuron and synapse computation, all while maintaining temporary peak system performance to achieve biological real-time operation of the system. A numerical model of this power management model is derived which allows DVFS architecture exploration for neuromorphics. The proposed technique is to be used for the second generation SpiNNaker neuromorphic many core system