920 research outputs found
Fast synchronization 3R burst-mode receivers for passive optical networks
This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed
CarRing IV- Real-time Computer Network
Ob in der Automobil-, Avionik- oder Automatisierungstechnik, die Fortschritte in der
Echtzeitkommunikation richten sich auf weitere Verbesserungen bereits existierender
Lösungen. Im Kfz-Bereich führen die steigenden Zahlen computerbasierter Systeme,
Anwendungen und Anschlüsse sowie die Verwendung mehrerer proprietärer Kommunikationsstandards zu einem immer komplexeren Kabelbaum. Ursächlich hierfür sind
inkompatible Standards, wodurch nicht nur die Kosten, sondern auch das Gewicht
und damit der Kraftstoffverbrauch negativ beeinflusst werden.
Im ersten Teil der Dissertation wird das Echtzeitprotokoll von CarRing IV (CRIV) vorgestellt. Es bietet isochrone und harte Echtzeitgarantien, ohne dass eine netzwerkweite Synchronisation erforderlich ist. Mit bis zu 16 Knoten pro Ring kann
ein CR-IV-Netz aus bis zu 256 Ringen bestehen, die durch Router miteinander verbunden sind. CR-IV verwendet ein reduziertes OSI-Modell (Schichten 1-3, 7), das
fĂĽr seine Anwendungsbereiche sowohl typisch als auch vorteilhaft ist. AuĂźerdem
unterstĂĽtzt es sowohl ereignis- als auch zeitgesteuerte Kommunikationsparadigmen.
Der Transparent-Modus ermöglicht es CR-IV, als Backbone für bestehende Netze
zu verwenden, wodurch Inkompatibilitätsprobleme beseitigt werden und der Wechsel zu einer einheitlicheren Netzlösung erleichtert wird. Mit dieser Funktionalität
können Nutzergeräte über ein CR-IV-Netz miteinander verbunden werden, ohne dass
der Nutzer eingreifen oder etwas ändern muss. Durch Multicast unterstützt CRIV auch die Emulation von Feldbussen. Der zweite Teil der Dissertation stellt den
anderen wichtigen Aspekt von CR-IV vor. Alle Schichten des OSI-Modells sind in
einem FPGA mit Hardware Description Languages (HDLs) ohne Hard- oder Softprozessoren implementiert. Das Register-Transfer-Level (RTL)-Hardwaredesign von
CR-IV wird mit einem neuen Ansatz erstellt, der am besten als tokenbasierter Datenfluss beschrieben werden kann. Der Ansatz ist sowohl vertikal als auch horizontal
skalierbar. Er verwendet lose gekoppelte Processing Elements (PEs), die stateless arbeiten, sowie Arbiter/Speicherzuordnungspaare. Durch die granulare Kontrolle und
die Aufteilung aller Aspekte einer Lösung eignet sich der Ansatz für die Implementierung anderer Software-Level-Lösungen in Hardware.
Viele Testszenarios werden durchgefĂĽhrt, um die in CR-IV erzielten Ergebnisse zu
verdeutlichen und zu überprüfen. Diese Szenarien reichen von direkten Leistungsmessungen bis hin zu verhaltensspezifischen Tests. Zusätzlich wird eine Labor-Demo
erstellt, die grundsätzlich auf ein Proof of Concept zielt. Die Demo stellt einen
praktischen Test anstelle szenariospezifischer Tests dar. Alle Testszenarien und die
Labor-Demo werden mit den Prototyp-Boards des Projekts durchgef¨uhrt, d.h. es sind
keine Simulationstests. Die Ergebnisse stellen die realistischen Leistungen von CR-IV
mit bis zu 13,61 Gbit/s dar.Whether be it automotive, avionics or automation, advances in their respective real-time communication technology focus on further improving preexisting solutions. For
in-vehicle communication, the ever-increasing number of computer-based systems,
applications and connections as well as the use of multiple proprietary communication
standards results in an increasingly complex wiring harness. This is in-part due to
those standards being incompatible with one another. In addition to cost, this also
impacts weight, which in turn affects fuel consumption.
The work presented in this thesis is in-part theoretical and in-part applied. The
former is represented by a new protocol, while the latter corresponds to the protocol’s
hardware implementation. In the first part of the thesis, the real-time communication protocol of CarRing IV (CR-IV) is presented. It provides isochronous and hard
real-time guarantees without requiring network-wide clock synchronization. With up
to 16 nodes per ring, a CR-IV network can consist of as many as 256 rings interconnected by routers. CR-IV uses a reduced OSI model (layers 1-3, 7), which is both
typical of and preferable for its application areas. Moreover, it supports both event- and time-triggered communication paradigms. The transparent mode feature allows
CR-IV to act as a backbone for existing networks, thereby addressing incompatibility
concerns and easing the transition into a more unified network solution. Using this
feature, user devices can communicate with one another via a CR-IV network without
requiring user interference, or any user device or application changes. Combined with
the protocol’s reliable multicast, the feature extends CR-IV’s capabilities to include
field bus emulation. The second part of the thesis presents the other important aspect
of CR-IV. All of its OSI model layers are implemented in a FPGA using Hardware
Description Languages (HDLs) without relying-on or including any hard or soft processors. CR-IV’s Register-Transfer Level (RTL) hardware design is created using a new
approach that can best be described as token-based data-flow. The approach is both
vertically and horizontally scalable. It uses stateless and loosely coupled Processing
Elements (PEs) as well as arbiter/memory allocation pairs. By having granular control and compartmentalizing every aspect of a solution, the approach lends itself to
being used for implementing other software-level solutions in hardware.
Many test scenarios are conducted to both highlight and examine the results
achieved in CR-IV. Those scenarios range from direct performance measurements to
behavior-specific tests. Moreover, a lab-demo is created that essentially amounts to
a proof of concept. The demo represents a practical test as opposed to a scenariospecific one. Whether be it test scenarios or the lab-demo, all are carried-out using the
project’s prototype boards, i.e. no simulation tests. The results obtained represent
CR-IV’s real-world realistic outcomes with up to 13.61 Gbps
A Fully Bidirectional Optical Network With Latency Monitoring Capability for the Distribution of Timing-Trigger and Control Signals in High-Energy Physics Experiments
The present paper discusses recent advances on a Passive Optical Network inspired Timing-Trigger and Control scheme for the future upgrade of the TTC system installed in the LHC experiments' and more specifically the currently known as TTCex to TTCrx link. The timing PON is implemented with commercially available FPGAs and 1-Gigabit Ethernet PON transceivers and provides a fixed latency gigabit downlink that can carry level-1 trigger accept decisions and commands as well as an upstream link for feedback from the front-end electronics
Clock Synchronized Transmission of 51.2GBd Optical Packets for Optically Switched Data Center Interconnects
Optical switching has attracted significant attention in recent research on data center networks (DCNs) as it is a promising viable route for the further scaling of hyper scale data centers, so that DCNs can keep pace with the rapid growth of machine-to-machine traffic. It has been shown that optical clock synchronization enables sub-nanosecond clock and data recovery time and is crucial to high performance optically switched DCN. Moreover, the interconnect data rate is expected to increase from the current 100 Gb/s per fiber to scale to 800 Gb/s and beyond, requiring high baud rate signaling at >50 GBd. Thus, future optically switched DCN should support >50GBd data transmission with optical clock synchronization. Here, we demonstrate the clock- synchronized transmission of 128-byte optical packets at 51.2 GBd and study the impact of reference clock phase noise on system performance, focusing on the tolerance to the clock phase misalignment that affects the system scalability and reliability. By comparing the tolerable sampling clock phase offsets using different reference clocks, we show that a clock phase offset window of about 8ps could be achieved with a <0.2ps source clock. Furthermore, we model and numerically study the de- correlation of clock phase noise. This allows the total jitter to be estimated, and thereby, the estimation of the transmission performance for future generations of high baud rate, clock synchronized DC interconnects
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