Bicontinuous minimal surface nanostructures for polymer blend solar cells

This paper presents the first examination of the potential for bicontinuous structures such as the gyroid structure to produce high efficiency solar cells based on conjugated polymers. The solar cell characteristics are predicted by a simulation model that shows how the morphology influences device performance through integration of all the processes occurring in organic photocells in a specified morphology. In bicontinuous phases, the surface de. ning the interface between the electron and hole transporting phases divides the volume into two disjoint subvolumes. Exciton loss is reduced because the interface at which charge separation occurs permeates the device so excitons have only a short distance to reach the interface. As each of the component phases is connected, charges will be able to reach the electrodes more easily. In simulations of the current-voltage characteristics of organic cells with gyroid, disordered blend and vertical rod (rods normal to the electrodes) morphologies, we find that gyroids have a lower than anticipated performance advantage over disordered blends, and that vertical rods are superior. These results are explored thoroughly, with geminate recombination, i.e. recombination of charges originating from the same exciton, identified as the primary source of loss. Thus, if an appropriate materials choice could reduce geminate recombination, gyroids show great promise for future research and applications

Electroencephalography (EEG)-Derived Markers to Measure Components of Attention Processing

Although extensively studied for decades, attention system remains an interesting challenge in neuroscience field. The Attention Network Task (ANT) has been developed to provide a measure of the efficiency for the three attention components identified in the Posner’s theoretical model: alerting, orienting and executive control. Here we propose a study on 15 healthy subjects who performed the ANT. We combined advanced methods for connectivity estimation on electroencephalographic (EEG) signals and graph theory with the aim to identify neuro-physiological indices describing the most important features of the three networks correlated with behavioral performances. Our results provided a set of band-specific connectivity indices able to follow the behavioral task performances among subjects for each attention component as defined in the ANT paradigm. Extracted EEG-based indices could be employed in future clinical applications to support the behavioral assessment or to evaluate the influence of specific attention deficits on Brain Computer Interface (BCI) performance and/or the effects of BCI training in cognitive rehabilitation applications

A Component-Based Middleware for a Reliable Distributed and Reconfigurable Spacecraft Onboard Computer

Emerging applications for space missions require increasing processing performance from the onboard computers. DLR's project “Onboard Computer - Next Generation” (OBC-NG) develops a distributed, reconfigurable computer architecture to provide increased performance while maintaining the high reliability of classical spacecraft computer architectures. Growing system complexity requires an advanced onboard middleware, handling distributed (realtime) applications and error mitigation by reconfiguration. The OBC-NG middleware follows the Component-Based Software Engineering (CBSE) approach. Using composite components, applications and management tasks can easily be distributed and relocated on the processing nodes of the network. Additionally, reuse of components for future missions is facilitated. This paper presents the flexible middleware architecture, the composite component framework, the middleware services and the model-driven Application Programming Interface (API) design of OBC-NG. Tests are conducted to validate the middleware concept and to investigate the reconfiguration efficiency as well as the reliability of the system. A relevant use case shows the advantages of CBSE for the development of distributed reconfigurable onboard software

Development and analysis of a verstile, reusable, high speed, DMA controller for custom embedded applications using the PCI bus

This thesis investigates the plausibility of designing and developing a versatile, reusable, high speed interface for custom computing applications, based on the Peripheral Component Interface (PCI) Bus. A PCI I/O board was developed, utilizing mainly Complex Programmable Logic Devices (CPLD\u27s), which included a custom Direct Memory Access (DMA) Controller to take advantage of the unique feature set of the PCI bus. The arbitration mechanisms and performance characteristics of the PCI bus are taken advantage of in order to achieve a maximum burst throughput rate of 66 Megabytes per second. Performance characteristics of the I/O board are analyzed for two separate PCI host systems. In the faster of the two systems, a 166MHz Pentium PC, a maximum aggregate throughput rate of 54 Megabytes per second for PCI burst writes was achieved. In all cases throughput increased as a function of transfer size. Due to buffering implementations in the host systems write performance was always superior to read performance. In addition to exceptional throughput capability, this implementation provides a design engineer with a versatile interface which can be mated to a number of high performance applications. The PCI I/O board\u27s external interface is implemented with a CPLD which can be quickly and easily modified to meet the needs of practically any custom interface without decreasing PCI bus performance. Using the on-board latency timer and programmable FIFO\u27s the board can be fine tuned to meet a variety of application requirements. The two main design goals were to provide unlimited bursting capability and to transfer 32-bits of data on every clock. The first was achieved through the implementation of a 32-bit burst Transfer Count register. The second goal had to be reduced by 50% due to a timing margin violation discovered during board debug

A framework for hierarchical scheduling on multiprocessors: from application requirements to run-time allocation

Hierarchical scheduling is a promising methodology for designing and deploying real-time applications, since it enables component-based design and analysis, and supports temporal isolation among competing applications. In hierarchical scheduling an application is described by means of a temporal interface. The designer faces the problem of how to derive the interface parameters so to make the application schedulable, at the same time minimizing the waste of computational resources. The problem is particularly relevant in multiprocessor systems, where it is not clear yet how the interface parameters influence the schedulability of the application and allocation on the physical platform. In this paper we present three novel contributions to hierarchical scheduling for multiprocessor systems. First, we propose the Bounded-Delay Multipartition (BDM), a new interface specification model that allows the designer to balance resource usage versus flexibility in selecting the virtual platform parameters. Second, we explore the schedulability region of a real-time application on top of a generic virtual platform, and derive the interface parameter. Finally, we propose Fluid Best-Fit, an algorithm that takes advantage of the extra degree of flexibility provided by the BDM to compute the virtual platform parameters and allocate it on the physical platform. The performance of the algorithm is evaluated by simulations

A Framework for Hierarchical Scheduling on Multiprocessors: From Application Requirements to Run-Time Allocation

Hierarchical scheduling is a promising methodology for designing and deploying real-time applications, since it enables component-based design and analysis, and supports temporal isolation among competing applications. In hierarchical scheduling an application is described by means of a temporal interface. The designer faces the problem of how to derive the interface parameters so to make the application schedulable, at the same time minimizing the waste of computational resources. The problem is particularly relevant in multiprocessor systems, where it is not clear yet how the interface parameters influence the schedulability of the application and allocation on the physical platform. In this paper we present three novel contributions to hierarchical scheduling for multiprocessor systems. First, we propose the Bounded-Delay Multipartition (BDM), a new interface specification model that allows the designer to balance resource usage versus flexibility in selecting the virtual platform parameters. Second, we explore the schedulability region of a real-time application on top of a generic virtual platform, and derive the interface parameter. Finally, we propose Fluid Best-Fit, an algorithm that takes advantage of the extra degree of flexibility provided by the BDM to compute the virtual platform parameters and allocate it on the physical platform. The performance of the algorithm is evaluated by simulations

RepComp - replicated software components for improved performance

Trabalho apresentado no âmbito do Mestrado em Engenharia Informática, como requisito parcial para obtenção do grau de Mestre em Engenharia InformáticaThe current trend of evolution in CPU architectures favours increasing the number of processing cores in lieu of improving the clock speed of an individual core. While improving clock rates automatically benefits any software executing on that processor, the same is not valid for adding new cores. To take advantage of an increased number of cores, software must include explicit support for parallel execution. This work explores a solution based on diverse replication which allows applications to transparently explore parallel processing power: macro-components. Applications typically make use of components with well-defined interfaces that have a number of possible underlying implementations with different characteristic. A macro-component is a component which encloses several of these implementations while offering the same interface as a regular implementation. Inside the macro-component,the implementations are used as replicas, and used to process any incoming operations. Using the best replica for each incoming operation, the macro-component is able to improve global performance. This dissertation provides an initial research on the use of these macro-components,detailing the technical challenges faced and proposing a design for the macro-component support system. Additionally, an implementation and subsequent validation of the proposed system are presented. These examples show that macro-components can achieve improved performance versus simple component implementations

GHOST: Building blocks for high performance sparse linear algebra on heterogeneous systems

While many of the architectural details of future exascale-class high performance computer systems are still a matter of intense research, there appears to be a general consensus that they will be strongly heterogeneous, featuring "standard" as well as "accelerated" resources. Today, such resources are available as multicore processors, graphics processing units (GPUs), and other accelerators such as the Intel Xeon Phi. Any software infrastructure that claims usefulness for such environments must be able to meet their inherent challenges: massive multi-level parallelism, topology, asynchronicity, and abstraction. The "General, Hybrid, and Optimized Sparse Toolkit" (GHOST) is a collection of building blocks that targets algorithms dealing with sparse matrix representations on current and future large-scale systems. It implements the "MPI+X" paradigm, has a pure C interface, and provides hybrid-parallel numerical kernels, intelligent resource management, and truly heterogeneous parallelism for multicore CPUs, Nvidia GPUs, and the Intel Xeon Phi. We describe the details of its design with respect to the challenges posed by modern heterogeneous supercomputers and recent algorithmic developments. Implementation details which are indispensable for achieving high efficiency are pointed out and their necessity is justified by performance measurements or predictions based on performance models. The library code and several applications are available as open source. We also provide instructions on how to make use of GHOST in existing software packages, together with a case study which demonstrates the applicability and performance of GHOST as a component within a larger software stack.Comment: 32 pages, 11 figure

An Integrated BiCMOS driver chip for medium power applications

The development of an integrated driver circuit intended for medium power switching applications is presented. The device contains, on one chip, CMOS digital control logic and bipolar drivers, with BiCMOS interface between the two technologies. The custom integrated circuit includes four outputs each capable of switching over 500 mA at 30 volts, at a frequency of up to 1 MHz. The development effort includes the design of the chip with its component circuits and cells. Standard cell CMOS logic gates along with drive and interface circuits were designed and characterized. An appropriate BiCMOS process was developed which utilizes an n-well based 4-micron polysilicon gate MOS technology and vertical NPNs with subcollector and double emitter implants. The chip performance specifications are evaluated with respect to technology requirements and device characteristics, and trade-offs in the design of the chip and the process are examined. Process and device modeling results are compared with the measured data, which show that the objectives of the design are successfully met for the various applications involving resistive, capacitive, and inductive loads

FPGA based Novel High Speed DAQ System Design with Error Correction

Present state of the art applications in the area of high energy physics experiments (HEP), radar communication, satellite communication and bio medical instrumentation require fault resilient data acquisition (DAQ) system with the data rate in the order of Gbps. In order to keep the high speed DAQ system functional in such radiation environment where direct intervention of human is not possible, a robust and error free communication system is necessary. In this work we present an efficient DAQ design and its implementation on field programmable gate array (FPGA). The proposed DAQ system supports high speed data communication (~4.8 Gbps) and achieves multi-bit error correction capabilities. BCH code (named after Raj Bose and D. K. RayChaudhuri) has been used for multi-bit error correction. The design has been implemented on Xilinx Kintex-7 board and is tested for board to board communication as well as for board to PC using PCIe (Peripheral Component Interconnect express) interface. To the best of our knowledge, the proposed FPGA based high speed DAQ system utilizing optical link and multi-bit error resiliency can be considered first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, critical path delay, efficiency and bit error rate (BER).Comment: ISVLSI 2015. arXiv admin note: substantial text overlap with arXiv:1505.04569, arXiv:1503.0881