On the van der Waerden numbers w(2;3,t)

We present results and conjectures on the van der Waerden numbers w(2;3,t) and on the new palindromic van der Waerden numbers pdw(2;3,t). We have computed the new number w(2;3,19) = 349, and we provide lower bounds for 20 <= t <= 39, where for t <= 30 we conjecture these lower bounds to be exact. The lower bounds for 24 <= t <= 30 refute the conjecture that w(2;3,t) <= t^2, and we present an improved conjecture. We also investigate regularities in the good partitions (certificates) to better understand the lower bounds. Motivated by such reglarities, we introduce *palindromic van der Waerden numbers* pdw(k; t_0,...,t_{k-1}), defined as ordinary van der Waerden numbers w(k; t_0,...,t_{k-1}), however only allowing palindromic solutions (good partitions), defined as reading the same from both ends. Different from the situation for ordinary van der Waerden numbers, these "numbers" need actually to be pairs of numbers. We compute pdw(2;3,t) for 3 <= t <= 27, and we provide lower bounds, which we conjecture to be exact, for t <= 35. All computations are based on SAT solving, and we discuss the various relations between SAT solving and Ramsey theory. Especially we introduce a novel (open-source) SAT solver, the tawSolver, which performs best on the SAT instances studied here, and which is actually the original DLL-solver, but with an efficient implementation and a modern heuristic typical for look-ahead solvers (applying the theory developed in the SAT handbook article of the second author).Comment: Second version 25 pages, updates of numerical data, improved formulations, and extended discussions on SAT. Third version 42 pages, with SAT solver data (especially for new SAT solver) and improved representation. Fourth version 47 pages, with updates and added explanation

A parallelization scheme based on work stealing for a class of sat solvers

Abstract. Due to the inherent NP-completeness of SAT, many SAT problems currently cannot be solved in a reasonable time. Usually, to tackle a new class of SAT problems, new ad-hoc algorithm must be designed. Another way to solve a new problem is to use a generic solver and employ parallelism to reduce the solve time. In this paper we propose a parallelization scheme for a class of SAT solvers based on the DPLL procedure. The scheme uses dynamic load balancing mechanism based on the work stealing techniques to deal with the irregularity of SAT problems. We parallelize Satz, one of the best generic SAT solvers, with the scheme to obtain a parallel solver called PSatz. The first experimental results on random 3-SAT and a set of well-known structured problems show the efficiency of PSatz. PSatz is freely available and runs on any networked workstations under Unix/Linux

Some Results in Extremal Combinatorics

Extremal Combinatorics is one of the central and heavily contributed areas in discrete mathematics, and has seen an outstanding growth during the last few decades. In general, it deals with problems regarding determination and/or estimation of the maximum or the minimum size of a combinatorial structure that satisfies a certain combinatorial property. Problems in Extremal Combinatorics are often related to theoretical computer science, number theory, geometry, and information theory. In this thesis, we work on some well-known problems (and on their variants) in Extremal Combinatorics concerning the set of integers as the combinatorial structure. The van der Waerden number w(k;t_0,t_1,...,t_{k-1}) is the smallest positive integer n such that every k-colouring of 1, 2, . . . , n contains a monochromatic arithmetic progression of length t_j for some colour j in {0,1,...,k-1}. We have determined five new exact values with k=2 and conjectured several van der Waerden numbers of the form w(2;s,t), based on which we have formulated a polynomial upper-bound-conjecture of w(2; s, t) with fixed s. We have provided an efficient SAT encoding for van der Waerden numbers with k>=3 and computed three new van der Waerden numbers using that encoding. We have also devised an efficient problem-specific backtracking algorithm and computed twenty-five new van der Waerden numbers with k>=3 using that algorithm. We have proven some counting properties of arithmetic progressions and some unimodality properties of sequences regarding arithmetic progressions. We have generalized Szekeres’ conjecture on the size of the largest sub-sequence of 1, 2, . . . , n without an arithmetic progression of length k for specific k and n; and provided a construction for the lower bound corresponding to the generalized conjecture. A Strict Schur number S(h,k) is the smallest positive integer n such that every 2-colouring of 1,2,...,n has either a blue solution to x_1 +x_2 +···+x_{h-1} = x_h where x_1 < x_2 < ··· < x_h, or a red solution to x_1+x_2+···+x_{k-1} =x_k where x_1 <x_2 <···<x_k. We have proven the exact formula for S(3, k)

Hardware Acceleration of Electronic Design Automation Algorithms

With the advances in very large scale integration (VLSI) technology, hardware is going parallel. Software, which was traditionally designed to execute on single core microprocessors, now faces the tough challenge of taking advantage of this parallelism, made available by the scaling of hardware. The work presented in this dissertation studies the acceleration of electronic design automation (EDA) software on several hardware platforms such as custom integrated circuits (ICs), field programmable gate arrays (FPGAs) and graphics processors. This dissertation concentrates on a subset of EDA algorithms which are heavily used in the VLSI design flow, and also have varying degrees of inherent parallelism in them. In particular, Boolean satisfiability, Monte Carlo based statistical static timing analysis, circuit simulation, fault simulation and fault table generation are explored. The architectural and performance tradeoffs of implementing the above applications on these alternative platforms (in comparison to their implementation on a single core microprocessor) are studied. In addition, this dissertation also presents an automated approach to accelerate uniprocessor code using a graphics processing unit (GPU). The key idea is to partition the software application into kernels in an automated fashion, such that multiple instances of these kernels, when executed in parallel on the GPU, can maximally benefit from the GPU?s hardware resources. The work presented in this dissertation demonstrates that several EDA algorithms can be successfully rearchitected to maximally harness their performance on alternative platforms such as custom designed ICs, FPGAs and graphic processors, and obtain speedups upto 800X. The approaches in this dissertation collectively aim to contribute towards enabling the computer aided design (CAD) community to accelerate EDA algorithms on arbitrary hardware platforms