Concatenated Turbo/LDPC codes for deep space communications: performance and implementation

Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals. Most of them rely on the concatenation of different codes that leads to high hardware implementation complexity and poor resource sharing. This work proposes a scheme based on the concatenation of non-custom LDPC and turbo codes that achieves excellent error correction performance. Moreover, since both LDPC and turbo codes can be decoded with the BCJR algorithm, our preliminary results show that an efficient hardware architecture with high resource reuse can be designe

Novel LDPC coding and decoding strategies: design, analysis, and algorithms

In this digital era, modern communication systems play an essential part in nearly every aspect of life, with examples ranging from mobile networks and satellite communications to Internet and data transfer. Unfortunately, all communication systems in a practical setting are noisy, which indicates that we can either improve the physical characteristics of the channel or find a possible systematical solution, i.e. error control coding. The history of error control coding dates back to 1948 when Claude Shannon published his celebrated work “A Mathematical Theory of Communication”, which built a framework for channel coding, source coding and information theory. For the first time, we saw evidence for the existence of channel codes, which enable reliable communication as long as the information rate of the code does not surpass the so-called channel capacity. Nevertheless, in the following 60 years none of the codes have been proven closely to approach the theoretical bound until the arrival of turbo codes and the renaissance of LDPC codes. As a strong contender of turbo codes, the advantages of LDPC codes include parallel implementation of decoding algorithms and, more crucially, graphical construction of codes. However, there are also some drawbacks to LDPC codes, e.g. significant performance degradation due to the presence of short cycles or very high decoding latency. In this thesis, we will focus on the practical realisation of finite-length LDPC codes and devise algorithms to tackle those issues. Firstly, rate-compatible (RC) LDPC codes with short/moderate block lengths are investigated on the basis of optimising the graphical structure of the tanner graph (TG), in order to achieve a variety of code rates (0.1 < R < 0.9) by only using a single encoder-decoder pair. As is widely recognised in the literature, the presence of short cycles considerably reduces the overall performance of LDPC codes which significantly limits their application in communication systems. To reduce the impact of short cycles effectively for different code rates, algorithms for counting short cycles and a graph-related metric called Extrinsic Message Degree (EMD) are applied with the development of the proposed puncturing and extension techniques. A complete set of simulations are carried out to demonstrate that the proposed RC designs can largely minimise the performance loss caused by puncturing or extension. Secondly, at the decoding end, we study novel decoding strategies which compensate for the negative effect of short cycles by reweighting part of the extrinsic messages exchanged between the nodes of a TG. The proposed reweighted belief propagation (BP) algorithms aim to implement efficient decoding, i.e. accurate signal reconstruction and low decoding latency, for LDPC codes via various design methods. A variable factor appearance probability belief propagation (VFAP-BP) algorithm is proposed along with an improved version called a locally-optimized reweighted (LOW)-BP algorithm, both of which can be employed to enhance decoding performance significantly for regular and irregular LDPC codes. More importantly, the optimisation of reweighting parameters only takes place in an offline stage so that no additional computational complexity is required during the real-time decoding process. Lastly, two iterative detection and decoding (IDD) receivers are presented for multiple-input multiple-output (MIMO) systems operating in a spatial multiplexing configuration. QR decomposition (QRD)-type IDD receivers utilise the proposed multiple-feedback (MF)-QRD or variable-M (VM)-QRD detection algorithm with a standard BP decoding algorithm, while knowledge-aided (KA)-type receivers are equipped with a simple soft parallel interference cancellation (PIC) detector and the proposed reweighted BP decoders. In the uncoded scenario, the proposed MF-QRD and VM-QRD algorithms are shown to approach optimal performance, yet require a reduced computational complexity. In the LDPC-coded scenario, simulation results have illustrated that the proposed QRD-type IDD receivers can offer near-optimal performance after a small number of detection/decoding iterations and the proposed KA-type IDD receivers significantly outperform receivers using alternative decoding algorithms, while requiring similar decoding complexity

Analysis of Minimal LDPC Decoder System on a Chip Implementation

This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation

Density Evolution for Asymmetric Memoryless Channels

Density evolution is one of the most powerful analytical tools for low-density parity-check (LDPC) codes and graph codes with message passing decoding algorithms. With channel symmetry as one of its fundamental assumptions, density evolution (DE) has been widely and successfully applied to different channels, including binary erasure channels, binary symmetric channels, binary additive white Gaussian noise channels, etc. This paper generalizes density evolution for non-symmetric memoryless channels, which in turn broadens the applications to general memoryless channels, e.g. z-channels, composite white Gaussian noise channels, etc. The central theorem underpinning this generalization is the convergence to perfect projection for any fixed size supporting tree. A new iterative formula of the same complexity is then presented and the necessary theorems for the performance concentration theorems are developed. Several properties of the new density evolution method are explored, including stability results for general asymmetric memoryless channels. Simulations, code optimizations, and possible new applications suggested by this new density evolution method are also provided. This result is also used to prove the typicality of linear LDPC codes among the coset code ensemble when the minimum check node degree is sufficiently large. It is shown that the convergence to perfect projection is essential to the belief propagation algorithm even when only symmetric channels are considered. Hence the proof of the convergence to perfect projection serves also as a completion of the theory of classical density evolution for symmetric memoryless channels.Comment: To appear in the IEEE Transactions on Information Theor

Optimized Bit Mappings for Spatially Coupled LDPC Codes over Parallel Binary Erasure Channels

In many practical communication systems, one binary encoder/decoder pair is used to communicate over a set of parallel channels. Examples of this setup include multi-carrier transmission, rate-compatible puncturing of turbo-like codes, and bit-interleaved coded modulation (BICM). A bit mapper is commonly employed to determine how the coded bits are allocated to the channels. In this paper, we study spatially coupled low-density parity check codes over parallel channels and optimize the bit mapper using BICM as the driving example. For simplicity, the parallel bit channels that arise in BICM are replaced by independent binary erasure channels (BECs). For two parallel BECs modeled according to a 4-PAM constellation labeled by the binary reflected Gray code, the optimization results show that the decoding threshold can be improved over a uniform random bit mapper, or, alternatively, the spatial chain length of the code can be reduced for a given gap to capacity. It is also shown that for rate-loss free, circular (tail-biting) ensembles, a decoding wave effect can be initiated using only an optimized bit mapper

Packet data communications over coded CDMA with hybrid type-II ARQ

This dissertation presents in-depth investigation of turbo-coded CDNIA systems in packet data communication terminology. It is divided into three parts; (1) CDMA with hybrid FEC/ARQ in deterministic environment, (2) CDMA with hybrid FEC/ARQ in random access environment and (3) an implementation issue on turbo decoding. As a preliminary, the performance of CDMA with hybrid FEC/ARQ is investigated in deterministic environment. It highlights the practically achievable spectral efficiency of CDMA system with turbo codes and the effect of code rates on the performance of systems with MF and LMMSE receivers, respectively. For given ensemble distance spectra of punctured turbo codes, an improved union bound is used to evaluate the error probability of ML turbo decoder with MF receiver and with LMMSE receiver front-end and, then, the corresponding spectral efficiency is computed as a function of system load. In the second part, a generalized analytical framework is first provided to analyze hybrid type-11 ARQ in random access environment. When applying hybrid type-11 ARQ, probability of packet success and packet length is generally different from attempt to attempt. Since the conventional analytical model, customarily employed for ALOHA system with pure or hybrid type-I ARQ, cannot be applied for this case, an expanded analytical model is introduced. It can be regarded as a network of queues and Jackson and Burke\u27s theorems can be applied to simplify the analysis. The second part is further divided into two sub topics, i.e. CDMA slotted ALOHA with hybrid type-11 ARQ using packet combining and CDMA unslotted ALOHA with hybrid type-11 ARQ using code combining. For code combining, the rate compatible punctured turbo (RCPT) codes are examined. In the third part, noticing that the decoding delay is crucial to the fast ARQ, a parallel MAP algorithm is proposed to reduce the computational decoding delay of turbo codes. It utilizes the forward and backward variables computed in the previous iteration to provide boundary distributions for each sub-block MAP decoder. It has at least two advantages over the existing parallel scheme; No performance degradation and No additional computation