Efficient and Robust Neuromorphic Computing Design

In recent years, brain inspired neuromorphic computing system (NCS) has been intensively studied in both circuit level and architecture level. NCS has demonstrated remarkable advantages for its high-energy efficiency, extremely compact space occupation and parallel data processing. However, due to the limited hardware resources, severe IR-Drop and process variation problems for synapse crossbar, and limited synapse device resolution, it’s still a great challenge for hardware NCS design to catch up with the fast development of software deep neural networks (DNNs). This dissertation explores model compression and acceleration methods for deep neural networks to save both memory and computation resources for the hardware implementation of DNNs. Firstly, DNNs’ weights quantization work is presented to use three orthogonal methods to learn synapses with one-level precision, namely, distribution-aware quantization, quantization regularization and bias tuning, to make image classification accuracy comparable to the state-ofthe-art. And then a two-step framework named group scissor, including rank clipping and group connection deletion methods, is presented to address the problems on large synapse crossbar consuming and high routing congestion between crossbars. Results show that after applying weights quantization methods, accuracy drop can be well controlled within negligible level for MNIST and CIFAR-10 dataset, compared to an ideal system without quantization. And for the group scissor framework method, crossbar area and routing area could be reduced to 8% (at most) of original size, indicating that the hardware implementation area has been saved a lot. Furthermore, the system scalability has been improved significantly

Stochastic-Based Computing with Emerging Spin-Based Device Technologies

In this dissertation, analog and emerging device physics is explored to provide a technology platform to design new bio-inspired system and novel architecture. With CMOS approaching the nano-scaling, their physics limits in feature size. Therefore, their physical device characteristics will pose severe challenges to constructing robust digital circuitry. Unlike transistor defects due to fabrication imperfection, quantum-related switching uncertainties will seriously increase their susceptibility to noise, thus rendering the traditional thinking and logic design techniques inadequate. Therefore, the trend of current research objectives is to create a non-Boolean high-level computational model and map it directly to the unique operational properties of new, power efficient, nanoscale devices. The focus of this research is based on two-fold: 1) Investigation of the physical hysteresis switching behaviors of domain wall device. We analyze phenomenon of domain wall device and identify hysteresis behavior with current range. We proposed the Domain-Wall-Motion-based (DWM) NCL circuit that achieves approximately 30x and 8x improvements in energy efficiency and chip layout area, respectively, over its equivalent CMOS design, while maintaining similar delay performance for a one bit full adder. 2) Investigation of the physical stochastic switching behaviors of Mag- netic Tunnel Junction (MTJ) device. With analyzing of stochastic switching behaviors of MTJ, we proposed an innovative stochastic-based architecture for implementing artificial neural network (S-ANN) with both magnetic tunneling junction (MTJ) and domain wall motion (DWM) devices, which enables efficient computing at an ultra-low voltage. For a well-known pattern recognition task, our mixed-model HSPICE simulation results have shown that a 34-neuron S-ANN implementation, when compared with its deterministic-based ANN counterparts implemented with digital and analog CMOS circuits, achieves more than 1.5 ~ 2 orders of magnitude lower energy consumption and 2 ~ 2.5 orders of magnitude less hidden layer chip area

Hardware implementation of a true random number generator integrating a hexagonal boron nitride memristor with a commercial microcontroller

The development of the internet-of-things requires cheap, light, small and reliable true random number generator (TRNG) circuits to encrypt the data-generated by objects or humans-before transmitting them. However, all current solutions consume too much power and require a relatively large battery, hindering the integration of TRNG circuits on most objects. Here we fabricated a TRNG circuit by exploiting stable random telegraph noise (RTN) current signals produced by memristors made of two-dimensional (2D) multi-layered hexagonal boron nitride (h-BN) grown by chemical vapor deposition and coupled with inkjet-printed Ag electrodes. When biased at small constant voltages (<= 70 mV), the Ag/h-BN/Ag memristors exhibit RTN signals with very low power consumption (similar to 5.25 nW) and a relatively high current on/off ratio (similar to 2) for long periods (>1 hour). We constructed TRNG circuits connecting an h-BN memristor to a small, light and cheap commercial microcontroller, producing a highly-stochastic, high-throughput signal (up to 7.8 Mbit s(-1)) even if the RTN at the input gets interrupted for long times up to 20 s, and if the stochasticity of the RTN signal is reduced. Our study presents the first full hardware implementation of 2D-material-based TRNGs, enabled by the unique stability and figures of merit of the RTN signals in h-BN based memristors

Hardware implementation of a true random number generator integrating a hexagonal boron nitride memristor with a commercial microcontroller

The development of the internet-of-things requires cheap, light, small and reliable true random number generator (TRNG) circuits to encrypt the data—generated by objects or humans—before transmitting them. However, all current solutions consume too much power and require a relatively large battery, hindering the integration of TRNG circuits on most objects. Here we fabricated a TRNG circuit by exploiting stable random telegraph noise (RTN) current signals produced by memristors made of two-dimensional (2D) multi-layered hexagonal boron nitride (h-BN) grown by chemical vapor deposition and coupled with inkjet-printed Ag electrodes. When biased at small constant voltages (≤70 mV), the Ag/h-BN/Ag memristors exhibit RTN signals with very low power consumption (∼5.25 nW) and a relatively high current on/off ratio (∼2) for long periods (>1 hour). We constructed TRNG circuits connecting an h-BN memristor to a small, light and cheap commercial microcontroller, producing a highly-stochastic, high-throughput signal (up to 7.8 Mbit s−1) even if the RTN at the input gets interrupted for long times up to 20 s, and if the stochasticity of the RTN signal is reduced. Our study presents the first full hardware implementation of 2Dmaterial- based TRNGs, enabled by the unique stability and figures of merit of the RTN signals in h-BN based memristors.Ministry of Science and Technology, China 2019YFE0124200 2018YFE0100800National Natural Science Foundation of China (NSFC) 61874075Collaborative Innovation Centre of Suzhou Nano Science and TechnologyPriority Academic Program Development of Jiangsu Higher Education Institutions111 Project from the State Administration of Foreign Experts Affairs of ChinaKing Abdullah University of Science & TechnologyMinisterio de Ciencia, Tecnologia e Innovacion (MINCyT) PICT 2016/0579 PME 2015-0196 PICTE 2018-0192 UTN-FRBA CCUTIBA4764TC MATUNBA4936 CCUTNBA5182 CCUTNBA661

Model Building and Security Analysis of PUF-Based Authentication

In the context of hardware systems, authentication refers to the process of confirming the identity and authenticity of chip, board and system components such as RFID tags, smart cards and remote sensors. The ability of physical unclonable functions (PUF) to provide bitstrings unique to each component can be leveraged as an authentication mechanism to detect tamper, impersonation and substitution of such components. However, authentication requires a strong PUF, i.e., one capable of producing a large, unique set of bits per device, and, unlike secret key generation for encryption, has additional challenges that relate to machine learning attacks, protocol attacks and constraints on device resources. We describe the requirements for PUF-based authentication, and present a PUF primitive and protocol designed for authentication in resource constrained devices. Our experimental results are derived from a 28 nm Xilinx FPGA. In the authentication scenario, strong PUFs are required since the adversary could collect a subset of challenges and response pairsto build a model and predict the responses for unseen challenges. Therefore, strong PUFs need to provide exponentially large challenge space and be resilient to model building attacks. We investigate the security properties of a Hardware-embedded Delay PUF called HELP which leverages within-die variations in path delays within a hardware-implemented macro (functional unit) as the entropy source. Several features of the HELP processing engine significantly improve its resistance to model-building attacks. We also investigate a novel technique that significantly improves the statistically quality of the generated bitstring for HELP. Stability across environmental variations such as temperature and voltage, is critically important for Physically Unclonable Functions (PUFs). Nearly all existing PUF systems to date need a mechanism to deal with “bit flips” when exact regeneration of the bitstring is required, e.g., for cryptographic applications. Error correction (ECC) and error avoidance schemes have been proposed but both of these require helper data to be stored for the regeneration process. Unfortunately, helper data adds time and area overhead to the PUF system and provides opportunities for adversaries to reverse engineer the secret bitstring. We propose a non-volatile memory-based (NVM) PUF that is able to avoid bit flips without requiring any type of helper data. We describe the technique in the context of emerging nano-devices, in particular, resistive random access memory (Memristor) cells, but the methodology is applicable to any type of NVM including Flash

A PUF based Lightweight Hardware Security Architecture for IoT

With an increasing number of hand-held electronics, gadgets, and other smart devices, data is present in a large number of platforms, thereby increasing the risk of security, privacy, and safety breach than ever before. Due to the extreme lightweight nature of these devices, commonly referred to as IoT or `Internet of Things\u27, providing any kind of security is prohibitive due to high overhead associated with any traditional and mathematically robust cryptographic techniques. Therefore, researchers have searched for alternative intuitive solutions for such devices. Hardware security, unlike traditional cryptography, can provide unique device-specific security solutions with little overhead, address vulnerability in hardware and, therefore, are attractive in this domain. As Moore\u27s law is almost at its end, different emerging devices are being explored more by researchers as they present opportunities to build better application-specific devices along with their challenges compared to CMOS technology. In this work, we have proposed emerging nanotechnology-based hardware security as a security solution for resource constrained IoT domain. Specifically, we have built two hardware security primitives i.e. physical unclonable function (PUF) and true random number generator (TRNG) and used these components as part of a security protocol proposed in this work as well. Both PUF and TRNG are built from metal-oxide memristors, an emerging nanoscale device and are generally lightweight compared to their CMOS counterparts in terms of area, power, and delay. Design challenges associated with designing these hardware security primitives and with memristive devices are properly addressed. Finally, a complete security protocol is proposed where all of these different pieces come together to provide a practical, robust, and device-specific security for resource-limited IoT systems

True random number generator based on the variability of the high resistance state of RRAMs

Hardware-based security primitives like True Random Number Generators (TRNG) have become a crucial part in protecting data over communication channels. With the growth of internet and cloud storage, TRNGs are required in numerous cryptographic operations. On the other hand, the inherently dense structure and low power characteristics of emerging nanoelectronic technologies such as resistive-switching memories (RRAM) make them suitable elements in designing hardware security modules integrated in CMOS ICs. In this paper, a memristor based TRNG is presented by leveraging the high stochasticity of RRAM resistance value in OFF (High Resistive) state. In the proposal, one or two devices can be used depending on whether the objective is focused on saving area or obtaining a higher random bit frequency generation. The generated bits, based on a combination of experimental measurements and SPICE simulations, passed all 15 National Institute of Standards and Technology (NIST) tests and achieved a throughput of tens of MHz.Postprint (published version