2 research outputs found
Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect
SRAM-based field programmable gate arrays (FPGAs) are widely used in mission-critical applications, such as aerospace and avionics. Due to the increasing working frequency and technology scaling of ultra-nanometer technology, single event transients (SETs) are becoming a major source of errors for these devices. In this paper, we propose a workflow for evaluating the behavior of SETs in SRAM-based FPGAs. The method is able to compute the propagation-induced pulse broadening (PIPB) effect introduced by the logic resources traversed by transient pulses. Besides, we developed an accurate look-up table (LUT) layout model able to effectively predict the kinds of the SETs induced by radiation-particle and to accurately mimic the phenomena of the SET generation and propagation. The proposed methodology is applicable to any recent technology to provide the SET analysis, necessary for an efficient mitigation technology. The experimental results achieved from a set of benchmark circuits mapped on a 28-nm SRAM-based FPGA and compared with the fault injection experiments demonstrate the effectiveness of our technique
Novel fault tolerant Multi-Bit Upset (MBU) Error-Detection and Correction (EDAC) architecture
Desde el punto de vista de seguridad, la certificaci贸n aeron谩utica de
aplicaciones cr铆ticas de vuelo requiere diferentes t茅cnicas que son usadas
para prevenir fallos en los equipos electr贸nicos. Los fallos de tipo hardware
debido a la radiaci贸n solar que existe a las alturas standard de vuelo, como
SEU (Single Event Upset) y MCU (Multiple Bit Upset), provocan un cambio
de estado de los bits que soportan la informaci贸n almacenada en memoria.
Estos fallos se producen, por ejemplo, en la memoria de configuraci贸n de
una FPGA, que es donde se definen todas las funcionalidades. Las t茅cnicas
de protecci贸n requieren normalmente de redundancias que incrementan el
coste, n煤mero de componentes, tama帽o de la memoria y peso.
En la fase de desarrollo de aplicaciones cr铆ticas de vuelo, generalmente
se utilizan una serie de est谩ndares o recomendaciones de dise帽o como
ABD100, RTCA DO-160, IEC62395, etc, y diferentes t茅cnicas de protecci贸n
para evitar fallos del tipo SEU o MCU. Estas t茅cnicas est谩n basadas en
procesos tecnol贸gicos espec铆ficos como memorias robustas, codificaciones
para detecci贸n y correcci贸n de errores (EDAC), redundancias software,
redundancia modular triple (TMR) o soluciones a nivel sistema.
Esta tesis est谩 enfocada a minimizar e incluso suprimir los efectos de los
SEUs y MCUs que particularmente ocurren en la electr贸nica de avi贸n como
consecuencia de la exposici贸n a radiaci贸n de part铆culas no cargadas (como
son los neutrones) que se encuentra potenciada a las t铆picas alturas de
vuelo. La criticidad en vuelo que tienen determinados sistemas obligan a que
dichos sistemas sean tolerantes a fallos, es decir, que garanticen un
correcto funcionamiento a煤n cuando se produzca un fallo en ellos. Es por
ello que soluciones como las presentadas en esta tesis tienen inter茅s en el
sector industrial.
La Tesis incluye una descripci贸n inicial de la f铆sica de la radiaci贸n
incidente sobre aeronaves, y el an谩lisis de sus efectos en los componentes
electr贸nicos aerona煤ticos basados en semiconductor, que desembocan en
la generaci贸n de SEUs y MCUs. Este an谩lisis permite dimensionar
adecuadamente y optimizar los procedimientos de correcci贸n que se
propongan posteriormente.
La Tesis propone un sistema de correcci贸n de fallos SEUs y MCUs que
permita cumplir la condici贸n de Sistema Tolerante a Fallos, a la vez que
minimiza los niveles de redundancia y de complejidad de los c贸digos de
correcci贸n. El nivel de redundancia es minimizado con la introducci贸n del
concepto propuesto HSB (Hardwired Seed Bits), en la que se reduce la
informaci贸n esencial a unos pocos bits semilla, neutros frente a radiaci贸n.
Los c贸digos de correcci贸n requeridos se reducen a la correcci贸n de un 煤nico
error, gracias al uso del concepto de Distancia Virtual entre Bits, a partir del
cual ser谩 posible corregir m煤ltiples errores simult谩neos (MCUs) a partir de
c贸digos simples de correcci贸n.
Un ejemplo de aplicaci贸n de la Tesis es la implementaci贸n de una
Protecci贸n Tolerante a Fallos sobre la memoria SRAM de una FPGA. Esto
significa que queda protegida no s贸lo la informaci贸n contenida en la
memoria sino que tambi茅n queda auto-protegida la funci贸n de protecci贸n
misma almacenada en la propia SRAM. De esta forma, el sistema es capaz
de auto-regenerarse ante un SEU o incluso un MCU, independientemente
de la zona de la SRAM sobre la que impacte la radiaci贸n. Adicionalmente,
esto se consigue con c贸digos simples tales como correcci贸n por bit de
paridad y Hamming, minimizando la dedicaci贸n de recursos de computaci贸n
hacia tareas de supervisi贸n del sistema.For airborne safety critical applications certification, different techniques
are implemented to prevent failures in electronic equipments. The HW
failures at flying heights of aircrafts related to solar radiation such as SEU
(Single-Event-Upset) and MCU (Multiple Bit Upset), causes bits alterations
that corrupt the information at memories. These HW failures cause errors, for
example, in the Configuration-Code of an FPGA that defines the
functionalities. The protection techniques require classically redundant
functionalities that increases the cost, components, memory space and
weight.
During the development phase for airborne safety critical applications,
different aerospace standards are generally recommended as ABD100,
RTCA-DO160, IEC62395, etc, and different techniques are classically used
to avoid failures such as SEU or MCU. These techniques are based on
specific technology processes, Hardened memories, error detection and
correction codes (EDAC), SW redundancy, Triple Modular Redundancy
(TMR) or System level solutions.
This Thesis is focussed to minimize, and even to remove, the effects of
SEUs and MCUs, that particularly occurs in the airborne electronics as a
consequence of its exposition to solar radiation of non-charged particles (for
example the neutrons). These non-charged particles are even powered at
flying altitudes due to aircraft volume. The safety categorization of different
equipments/functionalities requires a design based on fault-tolerant approach
that means, the system will continue its normal operation even if a failure
occurs. The solution proposed in this Thesis is relevant for the industrial
sector because of its Fault-tolerant capability.
Thesis includes an initial description for the physics of the solar radiation
that affects into aircrafts, and also the analyses of their effects into the
airborne electronics based on semiconductor components that create the
SEUs and MCUs. This detailed analysis allows the correct sizing and also
the optimization of the procedures used to correct the errors.
This Thesis proposes a system that corrects the SEUs and MCUs
allowing the fulfilment of the Fault-Tolerant requirement, reducing the
redundancy resources and also the complexity of the correction codes. The
redundancy resources are minimized thanks to the introduction of the
concept of HSB (Hardwired Seed Bits), in which the essential information is
reduced to a few seed bits, neutral to radiation. The correction codes
required are reduced to the correction of one error thanks to the use of the
concept of interleaving distance between adjacent bits, this allows the
simultaneous multiple error correction with simple single error correcting
codes.
An example of the application of this Thesis is the implementation of the
Fault-tolerant architecture of an SRAM-based FPGA. That means that the
information saved in the memory is protected but also the correction
functionality is auto protected as well, also saved into SRAM memory. In this
way, the system is able to self-regenerate the information lost in case of
SEUs or MCUs. This is independent of the SRAM area affected by the
radiation. Furthermore, this performance is achieved by means simple error
correcting codes, as parity bits or Hamming, that minimize the use of
computational resources to this supervision tasks for system.Programa Oficial de Doctorado en Ingenier铆a El茅ctrica, Electr贸nica y Autom谩ticaPresidente: Luis Alfonso Entrena Arrontes.- Secretario: Pedro Reviriego Vasallo.- Vocal: M陋 Luisa L贸pez Vallej