3 research outputs found
Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach
The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level
Resilient Design for Process and Runtime Variations
The main objective of this thesis is to tackle the impact of parameter variations in order to improve the chip performance and extend its lifetime