Detailed design specification for the ALT Shuttle Information Extraction Subsystem (SIES)

The approach and landing test (ALT) shuttle information extraction system (SIES) is described in terms of general requirements and system characteristics output products and processing options, output products and data sources, and system data flow. The ALT SIES is a data reduction system designed to satisfy certain data processing requirements for the ALT phase of the space shuttle program. The specific ALT SIES data processing requirements are stated in the data reduction complex approach and landing test data processing requirements. In general, ALT SIES must produce time correlated data products as a result of standardized data reduction or special purpose analytical processes. The main characteristics of ALT SIES are: (1) the system operates in a batch (non-interactive) mode; (2) the processing is table driven; (3) it is data base oriented; (4) it has simple operating procedures; and (5) it requires a minimum of run time information

A case for increased operating system support in chip multi-processors

Journal ArticleWe identify the operating system as one area where a novel architecture could significantly improve on current chip multi-processor designs, allowing increased performance and improved power efficiency. We first show that the operating system contributes a non-trivial overhead to even the most computationally intense workloads and that this OS contribution grows to a significant fraction of total instructions when executing interactive applications. We then show that architectural improvements have had little to no effect on the performance of the operating system over the last 15 years. Based on these observations we propose the need for increased operating system support in chip multiprocessors. Specifically we consider the potential of a separate Operating System Processor (OSP) operating concurrently with General Purpose Processors (GPP) in a Chip Multi-Processor (CMP) organization

A case for increased operating system support in chip multi-processors

Journal ArticleWe identify the operating system as one area where a novel architecture could significantly improve on current chip multi-processor designs, allowing increased performance and improved power efficiency. We first show that the operating system contributes a non-trivial overhead to even the most computationally intense workloads and that this OS contribution grows to a significant fraction of total instructions when executing interactive applications. We then show that architectural improvements have had little to no effect on the performance of the operating system over the last 15 years. Based on these observations we propose the need for increased operating system support in chip multiprocessors. Specifically we consider the potential of a separate Operating System Processor (OSP) operating concurrently with General Purpose Processors (GPP) in a Chip Multi-Processor (CMP) organization

DETC2005-85234 PERFORMANCE COMPARISONS OF TIMING TECHNIQUES IN A NON-REAL-TIME ENVIRONMENT

ABSTRACT General INTRODUCTION Data acquisition and control applications have traditionally relied on special-purpose hardware such as DSPs, FPGAs and ASICs to meet their deterministic timing needs. For many data acquisition and control applications, however, the timing requirements can easily be met by general-purpose computers whose clock frequencies have pushed into the gigahertz range and whose low cost makes them an attractive alternative to specialpurpose devices. For demanding applications, a real-time operating system must be used so that task completion deadlines can be guaranteed. For less demanding applications, general-purpose operating systems such as Microsoft Windows or Linux can be used. Regardless of the choice of operating system, generalpurpose computers still suffer from inherent non-determinis

VOSYSmonitor, a Low Latency Monitor Layer for Mixed-Criticality Systems on ARMv8-A

With the emergence of multicore embedded System on Chip (SoC), the integration of several applications with different levels of criticality on the same platform is becoming increasingly popular. These platforms, known as mixed-criticality systems, need to meet numerous requirements such as real-time constraints, Operating System (OS) scheduling, memory and OSes isolation. To construct mixed-criticality systems, various solutions, based on virtualization extensions, have been presented where OSes are contained in a Virtual Machine (VM) through the use of a hypervisor. However, such implementations usually lack hardware features to ensure a full isolation of other bus masters (e.g., Direct Memory Access (DMA) peripherals, Graphics Processing Unit (GPU)) between OSes. Furthermore on multicore implementation, one core is usually dedicated to one OS, causing CPU underutilization. To address these issues, this paper presents VOSYSmonitor, a multi-core software layer, which allows the co-execution of a safety-critical Real-Time Operating System (RTOS) and a non-critical General Purpose Operating System (GPOS) on the same hardware ARMv8-A platform. VOSYSmonitor main differentiation factors with the known solutions is the possibility for a processor to switch between secure and non-secure code execution at runtime. The partitioning is ensured by the ARM TrustZone technology, thus allowing to preserve the usage of virtualization features for the GPOS. VOSYSmonitor architecture will be detailed in this paper, while benchmarking its performance versus other known solutions

Analysis of Transaction Management Performance

There is currently much interest in incorporating transactions into both operating systems and general purpose programming languages. This paper provides a detailed examination of the design and performance of the“¢ transaction manager of the Camelot system. Camelot is a transaction facility that provides a rich model of transactions intended to support a wide variety of general-purpose applications. The transaction manager's principal function is to execute the protocols that ensure atomicity. The conclusions of this study are: a simple optimization to two-phase commit reduces logging activity of distributed transactions; non-blocking commit is practical for some applications; multithreaded design improves throughput provided that log batching is used; multi-casting reduces the variance of distributed commit protocols in a LAN environment; and the performance of transaction mechanisms such as Camelot depend heavily upon kernel performance

Real-time scheduling algorithms, task visualization

Real-time systems are computer systems that require responses to events within specified time limits or constraints. Many real-time systems are digital control systems comprised entirely of binary logic or a microprocessor dedicated to one software application that is its own operating system. In recent years, the reliability of general-purpose real-time operating systems (RTOS) consisting of a scheduler and system resource management have improved. In this project, I write a real-time simulator, a workload generator, analysis tools, several test cases, and run and interpret results. My experiments focus on providing evidence to support the claim that for the Rate Monotonic scheduling algorithm (RM), workloads with harmonically non-similar, periodic tasks are more difficult to schedule. The analysis tool I have developed is a measurement system and real-time simulator that analyzes real-time scheduling strategies. I have also developed a visualization system to display the scheduling decisions of a real-time scheduler. Using the measurement and visualization systems, I investigate scheduling algorithms for real-time schedulers and compare their performance. I run different workloads to test the scheduling algorithms and analyze what types of workload characteristics are preferred for real-time benchmarks

Observations on Instabilities of Cavitating Inducers

Hydraulic systems involving cavitating turbomachines are known to be susceptible to instabilities at certain critical operating conditions. Two distinct classes of cavitating inducer instabilities have been reported in the literature (Refs. 1-6). The purpose of this note is to report on some preliminary observations of these phenomena. The experiments were performed in the Dynamic Pump Test Facility (DPTF) at the California Institute of Technology (Refs. 7, 8). Results will be presented for two different inducers operating at different flow coefficients, [symbol] ([symbol]= mean axial velocity/inducer tip velocity- [equation]) and cavitation numbers, [symbol] ([symbol]=[equation]; where [equation] are the inlet and vapor pressures, and [symbol] is the liquid density). In general, the instabilities occurred just before the head breakdown. After head breakdown, the system tended to become stable again, although there were some indications of a second region of instability at very small cavitation numbers. Impeller IV is a quarter scale model of the Low Pressure Oxidizer Turbo-Pump (LPOTP) of the space shuttle main engine (Refs. 7, 8). The cavitation performance of this impeller is presented in Figure 1. Some of the mean operating states for which large, constant amplitude oscillations occurred in all the pressures and mass flow rates are indicated by stars. The cavitation in each of the blade passages oscillated in unison. This unstable behavior is termed auto-oscillation. The frequency of the auto-oscillations ranged from 28 to 35 Hz. As might be expected, there does exist a marginal region of operation for which the auto-oscillations have a time varying amplitude. These non-steady oscillations occurred as sporadic bursts of auto-oscillation. It was this feature that makes the boundaries of the auto-oscillation region difficult to define. In addition to the auto-oscillation observations on Impeller IV, two instances of "rotating cavitation" were observed and are labeled by boxes in Figure 1. The presence of rotating cavitation was determined by means of a stroboscope slaved to the rotational speed of the inducer. Rotating cavitation appeared as a non-stationary cavitation patterns which rotated with respect to the "fixed" inducer. (More recent testing has also revealed the existence of a stationary form of rotating cavitation sometime referred to as alternate blade cavitation.) The large amplitude disturbances in the upstream pressure and mass flow rates which characterized auto-oscillation were not observed during rotating cavitation. This suggests the rotating cavitation is most intimately associated with the dynamic characteristics of the cavitating inducer itself irrespective of the hydraulic system in which it resides

Maximizing multithreaded multicore architectures through thread migrations

Heterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a complexity-effective way to expose the heterogeneity in general-purpose workloads to the underlying hardware, in order to obtain all the potential performance of these architectures. In this paper we present the Heterogeneity-Aware Dynamic Thread Migrator (hDTM), a novel complexity-effective hardware mechanism that exposes the heterogeneity in software to the hardware, also enabling the hardware to react to the dynamic behavior variations in the running applications. By means of core-to-core thread migrations, the hDTM mechanism strives to perform the desired behavior transparently to the Operating System. As an example of the general-purpose hDTM concept presented in this paper, we describe a naive hDTM implementation for a Power5-like processor and provide results on the benefits of the proposed mechanism. Our results indicate that even this simple hDTM implementation is able to get close to hDTM’s goal, not only avoiding losses due to bad thread-to-core assignments (up to a 25%) but also going beyond the best static thread-to-core assignment upper limit.Postprint (published version

System-Level Design and Virtual Prototyping of a Telecommunication Application on a NUMA Platform

International audienceThe use of model-driven approaches for embedded system design has become a common practice. Among these model-driven approaches, only a few of them include the generation of a full-system simulation comprising operating system, code generation for tasks and hardware simulation models. Even less common is the extension to massively parallel, NoC based designs, such as required for high performance streaming applications where dozens of tasks are replicated onto identical general purpose processor cores of a Multi-processor System-on-chip (MP-SoC). We present the extension of a system-level tool to handle clustered Network-on-Chip (NoC) with virtual prototyping platforms. On the one hand, the automatic generation of the virtual prototype becomes more complex as topcell, address mapping and linker script have to be adapted. On the other hand, the exploration of the design space is particularly important for this class of applications, as performance may strongly be impacted by Non Uniform Memory Access (NUMA)