Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles

In this paper, a new time synchronization algorithm for OFDM systems with repetitive preamble is proposed. This algorithm makes use of coarse and fine time estimation; the fine time estimation is performed using a cross-correlation similar to previous proposals in the literature, whereas the coarse time estimation is made using a new metric and an iterative search of the last sample of the repetitive preamble. A complete analysis of the new metric is included, as well as a wide performance comparison, for multipath channel and carrier frequency offset, with the main time synchronization algorithms found in the literature. Finally, the complexity of the VLSI implementation of this proposal is discussed. © 2011 Springer Science+Business Media, LLC.This work was supported by the Spanish Ministerio de Educacion y Ciencia under grants TEC2006-14204-C02-01 and TEC2008-06787.Canet Subiela, MJ.; Almenar Terre, V.; Flores Asenjo, SJ.; Valls Coquillat, J. (2012). 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Preamble-based Symbol Timing Estimation for Wireless OFDM Systems

We propose a timing estimation scheme that reduces computational complexity while achieving performance comparable to the autocorrelation method commonly employed at the wireless receiver. The proposed method is based on the average magnitude difference function (AMDF). We present performance results for the proposed method for AWGN and Raleighfading channels in the context of IEEE 802.11a short preamble sequence. We also propose a preamble sequence based on Golomb sequence and compare its timing estimation performance with the IEEE 802.11a short-sequence. Simulation results show significant performance improvements for AWGN as well as Raleighfading channels

Design and implementation of synchronization and AGC for OFDM-based WLAN receivers

An efficient implementation of several tasks at the receiver becomes crucial in OFDM-based high-speed WLAN systems, such as automatic gain control, time and frequency synchronization and offset tracking. This paper deals with fixed point constraints and accuracy requirements for implementation of those algorithms. Also, a complete set of thresholds for the practical implementation of time and frequency synchronization sub-blocks is obtained. Moreover, a technique to mitigate the remaining frequency offset after coarse acquisition is proposed, yielding a good trade-off between performance and complexity. Finally, we propose the implementation of a simple and effective automatic gain control procedure.This work has been partially funded by Spanish government with project TIC 2002-03498 (ORISE), Telefonica I+D by the contract nº 25756, and the Chamber of Madrid Community and European Social Fund by a grant to the first author

System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude

Multi-user synchronisation in ad-hoc OFDM-based wireless personal area networks

In this paper, a procedure for dealing with the multi-user synchronisation problem in Orthogonal Frequency Division Multiple Access (OFDMA)-based systems for ad hoc environments is proposed and analysed. We show with this novel approach that it is possible to re-use much of the already extent literature for single-user synchronisation in OFDM and apply it to multi-user ad hoc scenarios. Also a distributed version of the procedure is proposed in order to fairly share out the power consumption among all the devices. The proposed procedure makes use of higher layer capabilities in a cross-layer design and it does not incur too much complexity or power. This issue is specially critical in wireless heterogeneous ad hoc networks where devices can be very limited in terms of transmission and/or computational power.Publicad

Scattered Pilots and Virtual Carriers Based Frequency Offset Tracking for OFDM Systems: Algorithms, Identifiability, and Performance Analysis

In this paper, we propose a novel carrier frequency offset (CFO) tracking algorithm for orthogonal frequency division multiplexing (OFDM) systems by exploiting scattered pilot carriers and virtual carriers embedded in the existing OFDM standards. Assuming that the channel remains constant during two consecutive OFDM blocks and perfect timing, a CFO tracking algorithm is proposed using the limited number of pilot carriers in each OFDM block. Identifiability of this pilot based algorithm is fully discussed under the noise free environment, and a constellation rotation strategy is proposed to eliminate the c-ambiguity for arbitrary constellations. A weighted algorithm is then proposed by considering both scattered pilots and virtual carriers. We find that, the pilots increase the performance accuracy of the algorithm, while the virtual carriers reduce the chance of CFO outlier. Therefore, the proposed tracking algorithm is able to achieve full range CFO estimation, can be used before channel estimation, and could provide improved performance compared to existing algorithms. The asymptotic mean square error (MSE) of the proposed algorithm is derived and simulation results agree with the theoretical analysis

FPGA implementation of an OFDM-based WLAN receiver

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5 dB for a PER = 10 -2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested. © 2011 Elsevier B.V. All rights reserved.This work was supported by the Spanish Ministerio de Educacion y Ciencia under grant TEC2008-06787.Canet Subiela, MJ.; Valls Coquillat, J.; Almenar Terré, V.; Marín-Roig Ramón, J. (2012). FPGA implementation of an OFDM-based WLAN receiver. Microprocessors and Microsystems. 36(3):232-244. https://doi.org/10.1016/j.micpro.2011.11.004S23224436