Maximizing the Efficiency using Montgomery Multipliers on FPGA in RSA Cryptography for Wireless Sensor Networks

The architecture and modeling of RSA public key encryption/decryption systems are presented in this work. Two different architectures are proposed, mMMM42 (modified Montgomery Modular Multiplier 4 to 2 Carry Save Architecture) and RSACIPHER128 to check the suitability for implementation in Wireless Sensor Nodes to utilize the same in Wireless Sensor Networks. It can easily be fitting into systems that require different levels of security by changing the key size. The processing time is increased and space utilization is reduced in FPGA due to its reusability. VHDL code is synthesized and simulated using Xilinx-ISE for both the architectures. Architectures are compared in terms of area and time. It is verified that this architecture support for a key size of 128bits. The implementation of RSA encryption/decryption algorithm on FPGA using 128 bits data and key size with RSACIPHER128 gives good result with 50% less utilization of hardware. This design is also implemented for ASIC using Mentor Graphics

Hardware Implementation of Parallel Modular Exponentiation Algorithm Based on Pipelining Technique

针对r-l模幂算法并行硬件实现成本高的问题,提出一种流水线形式的模幂运算结构。采用流水线技术对模幂算法中MOnTgOMEry模乘运算进行硬件设计,并由此构建模幂运算结构,实现并行模幂运算,降低硬件成本。同时对模幂算法中预处理和后处理步骤进行优化,以减少迭代次数。VIrTEX-2系列现场可编程门阵列原型的实现结果表明,在保证并行模幂运算速度的前提下,该结构的硬件实现成本近似为传统并行结构的1/2,且数据吞吐率更高,可达14 Mb/S。An efficient pipelined architecture is presented in this paper for solving the problem of high hardware cost of R-L modular exponentiation algorithm,which is formed of Montgomery modular multiplication built by using pipelining technique.The parallel calculation of algorithm can be executed and the hardware cost can be also reduced in the new architecture.Besides,two extra pre-processing and post-processing for converting an integer to its N-residue format in the conventional modular exponentiation algorithm are avoided to reduce the iteration time.The result shows that the new architecture can achieve high data throughput rate of more than 14 Mb/s on Xilinx Field Programmable Gata Array(FPGA) of Virtex-2 series when performs modular exponentiation,while occupy only about half hardware resources when compared with the conventional parallel architecture

FPGA Implementation of RSA algorithm and to develop a crypto based security system

This project is aimed to implement RSA algorithm on FPGA and to use the cryptography algorithm (RSA) to develop a crypto based security system. The control and data path of RSA algorithm (decryption only) is implemented on FPGA to behave as an independent password checker for the security system. The encryption part of the algorithm is done by the system itself. The system has the different public key for encryption for different users and the corresponding private key of the user is saved in the FPGA. The system generates a random 16-bit number and encrypts it using the encryption algorithm of RSA and sends the encrypted message to the FPGA using a USB to serial cable and the FPGA decrypts it using the decryption algorithm of FPGA and sends back the decrypted message to the system. The system checks the random message it generated before with the decrypted message send by FPGA for the particular user. If both the data matches then the system welcomes the user and if it doesn’t matches then it will give two more chances for entering the correct user name and connecting the correct FPGA