337 research outputs found
Coarse-grained reconfigurable array architectures
Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code
Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions
In the past decade, Convolutional Neural Networks (CNNs) have demonstrated
state-of-the-art performance in various Artificial Intelligence tasks. To
accelerate the experimentation and development of CNNs, several software
frameworks have been released, primarily targeting power-hungry CPUs and GPUs.
In this context, reconfigurable hardware in the form of FPGAs constitutes a
potential alternative platform that can be integrated in the existing deep
learning ecosystem to provide a tunable balance between performance, power
consumption and programmability. In this paper, a survey of the existing
CNN-to-FPGA toolflows is presented, comprising a comparative study of their key
characteristics which include the supported applications, architectural
choices, design space exploration methods and achieved performance. Moreover,
major challenges and objectives introduced by the latest trends in CNN
algorithmic research are identified and presented. Finally, a uniform
evaluation methodology is proposed, aiming at the comprehensive, complete and
in-depth evaluation of CNN-to-FPGA toolflows.Comment: Accepted for publication at the ACM Computing Surveys (CSUR) journal,
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Restoring the Broken Covenant Between Compilers and Deep Learning Accelerators
Deep learning accelerators address the computational demands of Deep Neural
Networks (DNNs), departing from the traditional Von Neumann execution model.
They leverage specialized hardware to align with the application domain's
structure. Compilers for these accelerators face distinct challenges compared
to those for general-purpose processors. These challenges include exposing and
managing more micro-architectural features, handling software-managed scratch
pads for on-chip storage, explicitly managing data movement, and matching DNN
layers with varying hardware capabilities. These complexities necessitate a new
approach to compiler design, as traditional compilers mainly focused on
generating fine-grained instruction sequences while abstracting
micro-architecture details. This paper introduces the Architecture Covenant
Graph (ACG), an abstract representation of an architectural structure's
components and their programmable capabilities. By enabling the compiler to
work with the ACG, it allows for adaptable compilation workflows when making
changes to accelerator design, reducing the need for a complete compiler
redevelopment. Codelets, which express DNN operation functionality and evolve
into execution mappings on the ACG, are key to this process. The Covenant
compiler efficiently targets diverse deep learning accelerators, achieving
93.8% performance compared to state-of-the-art, hand-tuned DNN layer
implementations when compiling 14 DNN layers from various models on two
different architectures
fpgaConvNet: A framework for mapping convolutional neural networks on FPGAs
Convolutional Neural Networks (ConvNets) are a powerful Deep Learning model, providing state-of-the-art accuracy to many emerging classification problems. However, ConvNet classification is a computationally heavy task, suffering from rapid complexity scaling. This paper presents fpgaConvNet, a novel domain-specific modelling framework together with an automated design methodology for the mapping of ConvNets onto reconfigurable FPGA-based platforms. By interpreting ConvNet classification as a streaming application, the proposed framework employs the Synchronous Dataflow (SDF) model of computation as its basis and proposes a set of transformations on the SDF graph that explore the performance-resource design space, while taking into account platform-specific resource constraints. A comparison with existing ConvNet FPGA works shows that the proposed fully-automated methodology yields hardware designs that improve the performance density by up to 1.62× and reach up to 90.75% of the raw performance of architectures that are hand-tuned for particular ConvNets
P2IP: A novel low-latency Programmable Pipeline Image Processor
International audienceThis paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P 2 IP. The P 2 IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurabil-ity of the P 2 IP enables it to perform a wide range of image pre-processing tasks directly on a pixel stream. The versatility of the P 2 IP is demonstrated through three image processing algorithms mapped onto the architecture, implemented in an FPGA-based platform. The obtained results show that the P 2 IP can achieve up to 129 fps in Full HD 1080p and 32 fps in 4K 2160p what makes it suitable for modern high-definition applications
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