1,131 research outputs found
ToPoliNano: Nanoarchitectures Design Made Real
Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologie
Asynchronous Nano-Electronics: Preliminary Investigation
This paper is a preliminary investigation in implementing
asynchronous QDI logic in molecular nano-electronics,
taking into account the restricted geometry, the lack of control
on transistor strengths, the high timing variations. We
show that the main building blocks of QDI logic can be successfully
implemented; we illustrate the approach with the
layout of an adder stage. The proposed techniques to improve
the reliability of QDI apply to nano-CMOS as well
CMOL: Second Life for Silicon?
This report is a brief review of the recent work on architectures for the
prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including
digital memories, reconfigurable Boolean-logic circuits, and mixed-signal
neuromorphic networks. The basic idea of CMOL circuits is to combine the
advantages of CMOS technology (including its flexibility and high fabrication
yield) with the extremely high potential density of molecular-scale
two-terminal nanodevices. Relatively large critical dimensions of CMOS
components and the "bottom-up" approach to nanodevice fabrication may keep CMOL
fabrication costs at affordable level. At the same time, the density of active
devices in CMOL circuits may be as high as 1012 cm2 and that they may provide
an unparalleled information processing performance, up to 1020 operations per
cm2 per second, at manageable power consumption.Comment: Submitted on behalf of TIMA Editions
(http://irevues.inist.fr/tima-editions
New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata
Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies,
promising alternative to CMOS technology due to faster speed, smaller size,
lower power consumption, higher scale integration and higher switching
frequency. Also, power dissipation is the main limitation of all the nano
electronics design techniques including the QCA. Researchers have proposed the
various mechanisms to limit this problem. Among them, reversible computing is
considered as the reliable solution to lower the power dissipation. On the
other hand, adders are fundamental circuits for most digital systems. In this
paper, Innovation is divided to three sections. In the first section, a method
for converting irreversible functions to a reversible one is presented. This
method has advantages such as: converting of irreversible functions to
reversible one directly and as optimal. So, in this method, sub-optimal methods
of using of conventional reversible blocks such as Toffoli and Fredkin are not
used, having of minimum number of garbage outputs and so on. Then, Using the
method, two new symmetric and planar designs of reversible full-adders are
presented. In the second section, a new symmetric, planar and fault tolerant
five-input majority gate is proposed. Based on the designed gate, a reversible
full-adder are presented. Also, for this gate, a fault-tolerant analysis is
proposed. And in the third section, three new 8-bit reversible
full-adder/subtractors are designed based on full-adders/subtractors proposed
in the second section. The results are indicative of the outperformance of the
proposed designs in comparison to the best available ones in terms of area,
complexity, delay, reversible/irreversible layout, and also in logic level in
terms of garbage outputs, control inputs, number of majority and NOT gates
A Complementary Resistive Switch-based Crossbar Array Adder
Redox-based resistive switching devices (ReRAM) are an emerging class of
non-volatile storage elements suited for nanoscale memory applications. In
terms of logic operations, ReRAM devices were suggested to be used as
programmable interconnects, large-scale look-up tables or for sequential logic
operations. However, without additional selector devices these approaches are
not suited for use in large scale nanocrossbar memory arrays, which is the
preferred architecture for ReRAM devices due to the minimum area consumption.
To overcome this issue for the sequential logic approach, we recently
introduced a novel concept, which is suited for passive crossbar arrays using
complementary resistive switches (CRSs). CRS cells offer two high resistive
storage states, and thus, parasitic sneak currents are efficiently avoided.
However, until now the CRS-based logic-in-memory approach was only shown to be
able to perform basic Boolean logic operations using a single CRS cell. In this
paper, we introduce two multi-bit adder schemes using the CRS-based
logic-in-memory approach. We proof the concepts by means of SPICE simulations
using a dynamical memristive device model of a ReRAM cell. Finally, we show the
advantages of our novel adder concept in terms of step count and number of
devices in comparison to a recently published adder approach, which applies the
conventional ReRAM-based sequential logic concept introduced by Borghetti et
al.Comment: 12 pages, accepted for IEEE Journal on Emerging and Selected Topics
in Circuits and Systems (JETCAS), issue on Computing in Emerging Technologie
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