Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit

Inverter-Based Low-Voltage CCII- Design and Its Filter Application

This paper presents a negative type second-generation current conveyor (CCII-). It is based on an inverter-based low-voltage error amplifier, and a negative current mirror. The CCII- could be operated in a very low supply voltage such as ±0.5V. The proposed CCII- has wide input voltage range (±0.24V), wide output voltage (±0.24V) and wide output current range (±24mA). The proposed CCII- has no on-chip capacitors, so it can be designed with standard CMOS digital processes. Moreover, the architecture of the proposed circuit without cascoded MOSFET transistors is easily designed and suitable for low-voltage operation. The proposed CCII- has been fabricated in TSMC 0.18μm CMOS processes and it occupies 1189.91 x 1178.43μm2 (include PADs). It can also be validated by low voltage CCII filters

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 µW. PSpice simulation results using the 0.18 µm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory

Single-input Multiple-output Tunable Log-domain Current-mode Universal Filter

This paper describes the design of a current-mode single-input multiple-output (SIMO) universal filter based on the log-domain filtering concept. The circuit is a direct realization of a first-order differential equation for obtaining the lossy integrator circuit. Lossless integrators are realized by log-domain lossy integrators. The proposed filter comprises only two grounded capacitors and twenty-four transistors. This filter suits to operate in very high frequency (VHF) applications. The pole-frequency of the proposed filter can be controlled over five decade frequency range through bias currents. The pole-Q can be independently controlled with the pole-frequency. Non-ideal effects on the filter are studied in detail. A validated BJT model is used in the simulations operated by a single power supply, as low as 2.5 V. The simulation results using PSpice are included to confirm the good performances and are in agreement with the theory

Voltage-Mode Multifunction Biquadratic Filters Using New Ultra-Low-Power Differential Difference Current Conveyors

This paper presents two low-power voltage-mode multifunction biquadratic filters using differential difference current conveyors. Each proposed circuit employs three differential difference current conveyors, two grounded capacitors and two grounded resistors. The low-voltage ultra-low-power differential difference current conveyor is used to provide low-power consumption of the proposed filters. By appropriately connecting the input and output terminals, the proposed filters can provide low-pass, band-pass, high-pass, band-stop and all-pass voltage responses at high-input terminals, which is a desirable feature for voltage-mode operations. The natural frequency and the quality factor can be orthogonally set by adjusting the circuit components. For realizing all the filter responses, no inverting-type input signal requirements as well as no component-matching conditional requirements are imposed. The incremental parameter sensitivities are also low. The characteristics of the proposed circuits are simulated by using PSPICE simulators to confirm the presented theory

An Octave-Range, Watt-Level, Fully-Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off-Efficiency Improvement

The power mixer array is presented as a novel power generation approach for non-constant envelope signals. It comprises several power mixer units that are dynamically turned on and off to improve the linearity and back-off efficiency. At the circuit level, the power mixer unit can operate as a switching amplifier to achieve high peak power efficiency. Additional circuit level linearization and back-off efficiency improvement techniques are also proposed. To demonstrate the feasibility of this idea, a fully-integrated octave-range CMOS power mixer array is implemented in a 130 nm CMOS process. It is operational between 1.2 GHz and 2.4 GHz and can generate an output power of +31.3 dBm into an external 50 Ω load with a PAE of 42% and a gain compression of only 0.4 dB at 1.8 GHz. It achieves a PAE of 25%, at an average output power of +26.4 dBm, and an EVM of 4.6% with a non-constant-envelope 16 QAM signal. It can also produce arbitrary signal levels down to -70 dBm of output power with the 16 QAM-modulated signal without any RF gain control circuit

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density. Previous hybrid analog CMOS-memristor approaches required extensive CMOS circuitry for training, and thus eliminated most of the density advantages gained by the adoption of memristor synapses. Further, they used different waveforms for pre and post-synaptic spikes that added undesirable circuit overhead. Here we describe a hardware architecture that can feature a large number of memristor synapses to learn real-world patterns. We present a versatile CMOS neuron that combines integrate-and-fire behavior, drives passive memristors and implements competitive learning in a compact circuit module, and enables in-situ plasticity in the memristor synapses. We demonstrate handwritten-digits recognition using the proposed architecture using transistor-level circuit simulations. As the described neuromorphic architecture is homogeneous, it realizes a fundamental building block for large-scale energy-efficient brain-inspired silicon chips that could lead to next-generation cognitive computing.Comment: This is a preprint of an article accepted for publication in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol 5, no. 2, June 201

Bandwidth aspects in second generation current conveyors

This paper discusses bandwidth problems associated with second-generation current conveyors (CCII). In particular, our work is centered in high-capacitance applications, and has been oriented for wireless optical links and applied physics. We discuss techniques for improving bandwidth in these CCIIs, and develop a new CCII structure with larger bandwidth than traditional circuits. These circuits are then compared in terms of their noise and dynamic range characteristics. A test circuit was developed to verify these different bandwidth behaviors

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe