Laminated ferrite memory system

Feasibility study of random access laminated ferrite memory system for spacecraft us

Electronics implementation of the solar neutron experiment

The electronic equipment design and function are discussed for the solar neutron counter experiment. Circuit diagrams are included

On board processor system study Final report

Development and characteristics of onboard processor syste

A large area detector for neutrons between 2 and 100 MeV

A neutron detector sensitive from 2 to 100 MeV is described. The detector is designed for high altitude balloon flight to measure the flux, energy and direction of albedo neutrons from the earth and to search for solar neutrons. A neutron scatter from a proton is required in each of two liquid scintillator tanks spaced 1 meter apart. The energy of the recoil proton in the first tank is obtained from pulse height analysis of the scintillator output. The energy of the recoil neutron is obtained from its time of flight between the tanks. The detector has been calibrated with 15.3 MeV neutrons and mu mesons. The minimum detectable flux is 10(-4) neutron/sq cm/sec at a counting rate of one per minute; the energy resolution is 12% at 15 MeV and 30% at 100 MeV. The angle between the incoming neutron and the recoil neutron is measured to + or - 10 deg

Manned maneuvering unit technology survey

The preliminary design of the manned maneuvering unit (MMU) for the shuttle is investigated, and the current state of the art in certain technology areas that may find application on the operational EVA shuttle MMU is examined. Three broad areas of technology, namely: (1) mechanical energy storage - i.e., the practicality of utilizing the energy storage capability of either a reaction wheel or a control moment gyro, (2) numerical and alphanumerical displays, and (3) recent electronics developments such as microprocessors and integrated injection logic, were covered

INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements

Level-1 Regional Calorimeter Trigger System for CMS

The Compact Muon Solenoid (CMS) calorimeter regional trigger system is designed to detect signatures of isolated and non-isolated electrons/photons, jets, ?-leptons, and missing and total transverse energy using a deadtimeless pipelined architecture. This system contains 18 crates of custom-built electronics. The pre-production prototype backplane, boards, links and Application-Specific Integrated Circuits (ASICs) have been built and their performance is characterized.Comment: Talk from the 2003 Computing in High Energy and Nuclear Physics (CHEP03), La Jolla, Ca, USA, March 2003, 6 pages, PDF. PSN THHT00

Study of radar pulse compression for high resolution satellite altimetry

Pulse compression techniques are studied which are applicable to a satellite altimeter having a topographic resolution of + 10 cm. A systematic design procedure is used to determine the system parameters. The performance of an optimum, maximum likelihood processor is analysed, which provides the basis for modifying the standard split-gate tracker to achieve improved performance. Bandwidth considerations lead to the recommendation of a full deramp STRETCH pulse compression technique followed by an analog filter bank to separate range returns. The implementation of the recommended technique is examined