3 research outputs found
Optimizing Data Intensive Flows for Networks on Chips
Data flow analysis and optimization is considered for homogeneous rectangular
mesh networks. We propose a flow matrix equation which allows a closed-form
characterization of the nature of the minimal time solution, speedup and a
simple method to determine when and how much load to distribute to processors.
We also propose a rigorous mathematical proof about the flow matrix optimal
solution existence and that the solution is unique. The methodology introduced
here is applicable to many interconnection networks and switching protocols (as
an example we examine toroidal networks and hypercube networks in this paper).
An important application is improving chip area and chip scalability for
networks on chips processing divisible style loads