Design of high performance frequency synthesizers in communication systems

Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption

A Modulator-less Beam Steering Transmitter based on a revised DDS-PLL Phase Shifter Architecture

This paper details the design and implementation of a modulator-less beam steering transmitter based on a revised DDS-PLL phase shifter architecture. The proposed topology targets low data rate communications for Internet-of-Things systems, and has been demonstrated using an FPGA evaluation board and a custom PCB with four PLLs centered at 2.453-GHz. Measured system performance for an experimental 32-kbps data rate achieved through a 16-PSK modulation scheme are discussed. The proposed architecture is frequency independent, can be used in multi-band devices and has the potential for being integrated as an RF System-on-Chip

A Modulator-less Beam Steering Transmitter based on a revised DDS-PLL Phase Shifter Architecture

This paper details the design and implementation of a modulator-less beam steering transmitter based on a revised DDS-PLL phase shifter architecture. The proposed topology targets low data rate communications for Internet-of-Things systems, and has been demonstrated using an FPGA evaluation board and a custom PCB with four PLLs centered at 2.453-GHz. Measured system performance for an experimental 32-kbps data rate achieved through a 16-PSK modulation scheme are discussed. The proposed architecture is frequency independent, can be used in multi-band devices and has the potential for being integrated as an RF System-on-Chip

A Fully Integrated Multi-Band Multi-Output Synthesizer with Wide-Locking-Range 1/3 Injection Locked Divider Utilizing Self-Injection Technique for Multi-Band Microwave Systems

This dissertation reports the development of a new multi-band multi-output synthesizer, 1/2 dual-injection locked divider, 1/3 injection-locked divider with phase-tuning, and 1/3 injection-locked divider with self-injection using 0.18-micrometer CMOS technology. The synthesizer is used for a multi-band multi-polarization radar system operating in the K- and Ka-band. The synthesizer is a fully integrated concurrent tri-band, tri-output phase-locked loop (PLL) with divide-by-3 injection locked frequency divider (ILFD). A new locking mechanism for the ILFD based on the gain control of the feedback amplifier is utilized to enable tunable and enhanced locking range which facilitates the attainment of stable locking states. The PLL has three concurrent multiband outputs: 3.47-4.313 GHz, 6.94-8.626 GHz and 19.44-21.42-GHz. High second-order harmonic suppression of 62.2 dBc is achieved without using a filter through optimization of the balance between the differential outputs. The proposed technique enables the use of an integer-N architecture for multi-band and microwave systems, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption. The 1/2 dual-ILFD with wide locking range and low-power consumption is analyzed and designed together with a divide-by-2 current mode logic (CML) divider. The 1/2 dual-ILFD enhances the locking range with low-power consumption through optimized load quality factor (QL) and output current amplitude (iOSC) simultaneously. The 1/2 dual-ILFD achieves a locking range of 692 MHz between 7.512 and 8.204 GHz. The new 1/2 dual-ILFD is especially attractive for microwave phase-locked loops and frequency synthesizers requiring low power and wide locking range. The 3.5-GHz divide-by-3 (1/3) ILFD consists of an internal 10.5-GHz Voltage Controlled Oscillator (VCO) functioning as an injection source, 1/3 ILFD core, and output inverter buffer. A phase tuner implemented on an asymmetric inductor is proposed to increase the locking range. The other divide-by-3 ILFD utilizes self-injection technique. The self-injection technique substantially enhances the locking range and phase noise, and reduces the minimum power of the injection signal needed for the 1/3 ILFD. The locking range is increased by 47.8 % and the phase noise is reduced by 14.77 dBc/Hz at 1-MHz offset

A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration

The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the phase lock loop (PLL) frequency synthesizer. In order to access various standards, the frequency synthesizer needs to have wide frequency tuning range, fast tuning speed, and low phase noise and frequency spur. The traditional analog charge pump frequency synthesizer circuit design is becoming diffcult due to the continuous down-scalings of transistor feature size and power supply voltage. The goal of this project was to develop an all digital phase locked loop (ADPLL) as the alternative solution technique in RF transceivers by taking advantage of digital circuitry\u27s characteristic features of good scalability, robustness against process variation and high noise margin. The targeted frequency bands for our ADPLL design included 880MHz-960MHz, 1.92GHz-2.17GHz, 2.3GHz-2.7GHz, 3.3GHz-3.8GHz and 5.15GHz-5.85GHz that are used by wireless communication standards such as GSM, UMTS, bluetooth, WiMAX and Wi-Fi etc. This project started with the system level model development for characterizing ADPLL phase noise, fractional spur and locking speed. Then an on-chip jitter detector and parameter adapter was designed for ADPLL to perform self-tuning and self-calibration to accomplish high frequency purity and fast frequency locking in each frequency band. A novel wide band DCO is presented for multi-band wireless application. The proposed wide band adaptive ADPLL was implemented in the IBM 0.13µm CMOS technology. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was assessed and agrees well with the theoretical analysis

8-12 GHz pHEMT MMIC Low-Noise Amplifier for 5G and Fiber-Integrated Satellite Applications

The fifth-generation (5G) radio access technology promises to revolutionise integrated earth-space communications applications for ubiquitous, seamless and broadband services. The assigned sub-6 GHz and millimetre-wave 5G frequencies require the sensitivity of the receiver front-end subsystem(s) to detect and amplify the desired signal at a noise floor of less than -90 dBm for a cost-effective infrastructure deployment. This paper presents a broadband monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) design based on a 0.15 µm gate length Indium Gallium Arsenide (InGaAs) pseudomorphic high electron mobility transistor (pHEMT) technology for 5G and fiber-integrated satellite communications applications. The designed three-stage 8-12 GHz LNA implements a common-source topology. The MMIC LNA subsystem performance demonstrates an industry-leading in-band gain response of 40 dB; a noise figure of 1.0 dB; and a power dissipation of 43 mW. For a constant bandwidth receiver, the sensitivity changes by approximately 1.5 dB over the operating satellite signal frequency. Similarly, for a variable bandwidth receiver, the sensitivity changes by approximately 1.5 dB over the channel bandwidth. Moreover, the sensitivity margin of the designed LNA is 40 dB and this holds a great promise for real-time radio access component-level reconfiguration applications

Development of microwave and millimeter-wave integrated-circuit stepped-frequency radar sensors for surface and subsurface profiling

Two new stepped-frequency continuous wave (SFCW) radar sensor prototypes, based on a coherent super-heterodyne scheme, have been developed using Microwave Integrated Circuits (MICs) and Monolithic Millimeter-Wave Integrated Circuits (MMICs) for various surface and subsurface applications, such as profiling the surface and subsurface of pavements, detecting and localizing small buried Anti-Personnel (AP) mines and measuring the liquid level in a tank. These sensors meet the critical requirements for subsurface and surface measurements including small size, light weight, good accuracy, fine resolution and deep penetration. In addition, two novel wideband microstrip quasi-TEM horn antennae that are capable of integration with a seamless connection have also been designed. Finally, a simple signal processing algorithm, aimed to acquire the in-phase (I) and quadrature (Q) components and to compensate for the I/Q errors, was developed using LabView. The first of the two prototype sensors, named as the microwave SFCW radar sensor operating from 0.6-5.6-GHz, is primarily utilized for assessing the subsurface of pavements. The measured thicknesses of the asphalt and base layers of a pavement sample were very much in agreement with the actual data with less than 0.1-inch error. The measured results on the actual roads showed that the sensor accurately detects the 5-inch asphalt layer of the pavement with a minimal error of 0.25 inches. This sensor represents the first SFCW radar sensor operating from 0.6-5.6-GHz. The other sensor, named as the millimeter-wave SFCW radar sensor, operates in the 29.72-35.7-GHz range. Measurements were performed to verify its feasibility as a surface and sub-surface sensor. The measurement results showed that the sensor has a lateral resolution of 1 inch and a good accuracy in the vertical direction with less than  0.04-inch error. The sensor successfully detected and located AP mines of small sizes buried under the surface of sand with less than 0.75 and 0.08 inches of error in the lateral and vertical directions, respectively. In addition, it also verified that the vertical resolution is not greater than 0.75 inches. This sensor is claimed as the first Ka-band millimeter-wave SFCW radar sensor ever developed for surface and subsurface sensing applications

Energy-efficient clock generation for communication and computing systems using injection locking

The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases. A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals. A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed