A 90μW 12MHz Relaxation Oscillator with a -162dB FOM

A relaxation oscillator exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. A 65nm CMOS design produces a sawtooth waveform, has a frequency tuning range of 1 to 12MHz and a constant frequency-tuning gain. By minimizing and balancing noise contributions from charge and discharge mechanisms, a FOM of -162dB is achieved, which is a 7dB improvement over state-of-the-art

A 12MHz Switched-Capacitor Relaxation Oscillator with a Nearly Minimal FoM of -161dBc/Hz

In this work the phase noise performance of relaxation oscillators has been analyzed resulting in simple though precise phase noise expressions. These expressions have lead to a new relaxation oscillator topology, which exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. Measurements on a 65nm CMOS design show a sawtooth waveform, a frequency tuning range between 1 and 12MHz and a rather constant frequency tuning gain. At 12MHz oscillation frequency it consumes 90μW while the phase noise is -109dBc/Hz at 100KHz offset frequency. By minimizing and balancing noise contributions of charge and discharge mechanisms, a nearly minimal FoM of -161dBc/Hz has been achieved, which is a 6dB improvement over state-of-the-art

A 65-nm CMOS Temperature-Compensated Mobility-Based Frequency reference for wireless sensor networks

For the first time, a temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55°C to 125 °C, its frequency spread is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm2 and draws 42.6 μA from a 1.2-V supply at room temperature.\ud \u

The Design and Construction of an Infrared Activated Security System at 9 KHz Frequency

This paper reports the design and construction of a security system. The system will produce sound of a barking dog at audible frequency of 9 KHz. The design procedure and principle of operation of the various modules as presented in this work are based on the locally available electronic component

A Coupled Sawtooth Oscillator combining Low Jitter and High Control Linearity

A new type of current controlled oscillator (CCO) is presented that combines excelllent control linearity with low timing jitter. The problem of overshoot in traditional relaxation oscillators is solved by using an alternative for the Schmitt-trigger. Circuits realised in a 0.8µm CMOS process show a HD2 < -65dB and HD3 < -85 dB (¿f=500 kHz). The measured phase noise is smaller than -100dBc/Hz at 10kHz carrier offset frequency at FOSC=1.5 MHz for a supply current of 360µA

Towards minimum achievable phase noise of relaxation oscillators

A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation-oscillator loop can be prevented from contributing to 1/f2 colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched-capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65 nm CMOS process, occupying 200 µm × 150 µm. Its frequency tuning range is 1–12 MHz, and its phase noise is L(100kHz) = −109dBc/Hz at fosc = 12MHz, while consuming 90 μW. A figure of merit of −161dBc/Hz is achieved, which is only 4 dB from the theoretical limit

Thermoelectric Power Harvesting for Biomedical Implants

The modern healthcare industry relies on the use of implantable monitoring devices to obtain potentially life-saving data. This has led to the necessity for small, long-lasting batteries to be used in these devices. In order to replace a device’s battery, patients often undergo invasive surgery. This surgery can be costly and physically strenuous for the patient; thus, there is a desire to minimize the frequency of battery replacement. The goal of this research is to develop an integrated circuit that can supply harvested energy to an implantable monitoring device so as to extend implant batteries’ lifetime. These monitoring devices are often implanted just below the skin of a patient, where natural temperature gradients exist. Using the well-known physical principle called the Seebeck effect, these temperature gradients can be exploited to produce electrical power by using a specialized device called a thermoelectric generator. With some additional circuitry, this harvested energy can be used in place of the battery to supply power to the implanted device. Such circuitry includes a switching regulator with a PWM controller, an oscillator, and digital logic. The thermoelectric generator can harvest enough energy to power the device, but the voltage produced is generally too low to be used. Thus, the voltage must be stepped up to a higher value. The switching regulator topology best suited for this purpose is the DC-DC boost converter due to its high efficiency. However, the amount of power harvested is small, so this paper has a major emphasis on power consumption optimization for each circuit block added. Also, the boost converter must use feedback in order to regulate the output to a constant voltage, so a controller was designed and implemented for this purpose. An additional feedforward path was added to perform an impedance match between the source resistance and the boost converter to reduce the charge time of the output capacitor. An oscillator was needed to switch transistors in the boost converter and provide the synchronicity needed in the digital logic blocks. Finally, the last circuitry developed was digital logic to control the startup procedure and choose to use either the harvested energy or the battery to power the implanted device. This paper will discuss the design procedure for each of the mentioned circuit blocks and provide the results of the research conducted

Design of an RC Oscillator for Automotive Applications

Tato práce je zaměřena na návrh integrovaného relaxačního oscilátoru pro automobilové aplikace, které jsou charakteristické extrémními provozními podmínkami a vysokými požadavky na robustnost. Z dostupné literatury byla provedena rešerše, která umožnila postihnout nezbytný teoretický základ pro komparativní studii nedávno představených designů integrovaných oscilátorů a také pomohla navrhnout architekturu oscilátoru, která v implementaci zahrnuje princip IEF. Za účelem předpovězení negativních vlivů na výkon systému a optimálních parametrů bloků byly provedeny simulace vysokoúrovňového modelu. V práci je diskutována implementace jednotlivých bloků a prezentovány výsledky simulace kritických parametrů. Simulace navrženého oscilátoru prokázaly konzistenci konceptu IEF pro praktickou realizaci. Realizovaný systém však potřebuje další vylepšení.The thesis is aimed on the integrated relaxation oscillator design for automotive applications, that are characterized by harsh operation conditions and high robustness requirements. Literature research was conducted to acquire necessary theoretical basis for comparative study of the recently proposed integrated oscillator designs to choose the oscillator architecture utilizing integrated-error feedback for the implementation. High-level model simulations were conducted to predict negative influences on the system performance and to suggest blocks optimal parameters for the design. The implementation of the designed blocks was discussed, and simulation results of the critical parameters were presented. The designed oscillator simulations proved the consistency of the integrated-error feedback concept for practical realization. However, the designed system needs further improvements

Real time analysis of voiced sounds

A power spectrum analysis of the harmonic content of a voiced sound signal is conducted in real time by phase-lock-loop tracking of the fundamental frequency, (f sub 0) of the signal and successive harmonics (h sub 1 through h sub n) of the fundamental frequency. The analysis also includes measuring the quadrature power and phase of each frequency tracked, differentiating the power measurements of the harmonics in adjacent pairs, and analyzing successive differentials to determine peak power points in the power spectrum for display or use in analysis of voiced sound, such as for voice recognition