In this work the phase noise performance of relaxation oscillators has been analyzed resulting in simple though precise phase noise expressions. These expressions have lead to a new relaxation oscillator topology, which exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. Measurements on a 65nm CMOS design show a sawtooth waveform, a frequency tuning range between 1 and 12MHz and a rather constant frequency tuning gain. At 12MHz oscillation frequency it consumes 90μW while the phase noise is -109dBc/Hz at 100KHz offset frequency. By minimizing and balancing noise contributions of charge and discharge mechanisms, a nearly minimal FoM of -161dBc/Hz has been achieved, which is a 6dB improvement over state-of-the-art

Geraedts, P.F.J.

Klumperink, E.A.M.

Nauta, B.

Tuijl, A.J.M. van

Wienk, G.J.M.

English

van Tuijl, Adrianus Johannes Maria

Klumperink, Eric A.M.

Wienk, Gerhardus J.M.

Nauta, Bram

NARCIS 

A 12MHz Switched-Capacitor Relaxation Oscillator with a Nearly Minimal FoM of -161dBc/Hz

University of Twente Research Information

 1A 12MHz Switched-Capacitor Relaxation Oscillator with a Nearly Minimal FoM of -161dBc/Hz Paul F.J. Geraedts, Ed A.J.M. van Tuijl, E.A.M. Klumperink, G.J.M. Wienk and B. Nauta   Abstract— In this work the phase noise performance of relaxation oscillators has been analyzed resulting in simple though precise phase noise expressions. These expressions have lead to a new relaxation oscillator topology, which exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. Measurements on a 65nm CMOS design show a sawtooth waveform, a frequency tuning range between 1 and 12MHz and a rather constant frequency tuning gain. At 12MHz oscillation frequency it consumes 90μW while the phase noise is -109dBc/Hz at 100KHz offset frequency. By minimizing and balancing noise contributions of charge and discharge mechanisms, a nearly minimal FoM of -161dBc/Hz has been achieved, which is a 6dB improvement over state-of-the-art.  Index Terms— figure of merit, phase noise, relaxation oscillators, thermodynamics I. INTRODUCTION LOCK generation is an important area in integrated circuit design. Both LC oscillators and RC oscillators are frequently applied in this area. Ring oscillators and relaxation oscillators are both subsets of RC oscillators featuring large tuning ranges and small areas. Fig. 1 shows a typical relaxation oscillator with a capacitor and two switched current sources.  Such relaxation oscillators have two advantages with respect to ring oscillators: 1) they have a constant frequency tuning gain; and 2) their phase can be read out continuously due to their triangular (or sawtooth) waveform. A major disadvantage of practical relaxation oscillators is their poor phase noise performance compared to ring oscillators [1], [2], [4]. This phase noise performance is the main focus of this paper. First Section II will show typical phase noise performance of ring oscillators and relaxation oscillators. Section III will then present a new relaxation oscillator topology which shows very good phase noise performance. Section IV discusses the transistor implementation and simulation results and Section V discusses the IC implementation and measurement results. Section VI finally draws conclusions.  The authors are with the IC-Design Group, CTIT, University of Twente, Enschede, Netherlands (e-mail: p.f.j.geraedts@utwente.nl). E. van Tuijl is also with Axiom IC Twente, Enschede, Netherlands (e-mail: ed.van.tuijl@axiom-ic.com).  II. OSCILLATOR FIGURE OF MERIT The 1/f2 phase noise performance of oscillators can be compared using the figure of merit definition [1].   [dBc/Hz]1mWPff)£(flog10FoM core2oscmm ⎟⎟⎠⎞⎜⎜⎝⎛⎟⎟⎠⎞⎜⎜⎝⎛=  (1)  £(fm) is the well-known single-sideband phase noise measure. fosc is the oscillation frequency and fm is the offset frequency with respect to this oscillation frequency. Pcore is the power consumed by the oscillator core.  Navid et al. have shown that at 290K thermodynamics limits the FoM of ring oscillators and relaxation oscillators to  -165.3dBc/Hz and -169.1dBc/Hz, respectively [2]. Interestingly, they have also shown that the FoM of practical ring oscillators is generally better than about -160dBc/Hz, while the FoM of practical relaxation oscillators is about 10dB worse. So in theory relaxation oscillators can be better, but in practice they are not.  Part of the explanation is given in [2]; the noise added by the comparator, which is present in relaxation oscillators (cmposc in Fig. 1) but not in ring oscillators, increases the phase noise. We will now show that by filtering this noise by exploiting a switched-capacitor discharge mechanism, the FoM of a practical relaxation oscillator can be as good as the FoM of ring oscillators. III. SWITCHED-CAPACITOR RELAXATION OSCILLATOR A. Operation Fig. 2 shows the new relaxation oscillator. As in Fig. 1, I1 charges capacitor C1. However, C1 is not grounded, but connected across an OTA, and the discharge process exploits a switched capacitor, C2, which is reversed periodically. The operation of the circuit is described in the next sentences.  The initial voltage across C2 is Vref,OTA. At t0, I1 is charging C1 at a constant rate via the OTA, resulting in a linearly decreasing voltage V-. At t1, V- crosses Vref,osc and cmposc reverses C2. C2 is then being charged from –Vref,OTA to +Vref,OTA by I1 and the OTA. At t2, C2 is charged to +Vref,OTA and, as a C175 2result, a fixed charge packet equal to 2C2Vref,OTA has been subtracted from C1. V3 = V+ - V- is a sawtooth waveform. Subtracting this fixed charge packet filters out the noise of the oscillator comparator. The operation is illustrated in Fig. 3, which shows the control signal X, V3 and the output of the comparator cmpout, Vout, is also shown, which produces an edge whenever voltage V3 reverses polarity. Suppose now that cmposc is noisy and C2 is reversed at t4 instead of at t3. Although the duty cycle of Vout is changed (at t5), the active edge of Vout at t6 is unaffected and so is the phase noise.  This filter technique is similar to the anti-jitter circuit (AJC) technique used in open-loop jitter filters [3]; note that we apply a switched-capacitor circuit to subtract the charge packet, which is very power-efficient.  B. Phase Noise Performance Filtering out the noise of the oscillator comparator has two consequences: 1) the power dissipated by the oscillator comparator and its reference can be reduced without deteriorating the phase noise; and 2) the two remaining contributions to the 1/f2 phase noise are the white noise of the charging and discharging mechanisms. It can be shown that the resulting FoM of such a relaxation oscillator is given by (2).   Fig. 1. Relaxation oscillator based on current sources (which is part of thegeneral class of relaxation oscillators based on resistors, like in [2]).     Fig. 3. Technique to filter out the noise of the oscillator comparator (cmposc).  dBc/Hz][ΔVΔVΔVΔV1mWIP2kTlog10FoM21211core⎟⎟⎠⎞⎜⎜⎝⎛⋅+⋅⋅⋅=  (2)  k is the Boltzmann constant, T is the absolute temperature and Pcore is the power consumed by the oscillator core: Pcore = VDDIcore. I1 is the charge current and ΔV1 and ΔV2 (also shown in Fig. 2) are the voltage headroom reserved for the charging and the discharging mechanisms, respectively. For a good FoM we want ΔV1 and ΔV2 to be high and about equal, while we also want a large V3 swing to reduce the phase noise floor contribution of cmpout. In Fig. 1 this is not possible, since the sum ΔV1 + ΔV2 + ΔV3 has to fit in the supply VDD. In Fig. 2 the voltage swing of V3 mainly occurs at the output of the OTA, leaving the full VDD for ΔV1 + ΔV2. Instead of reversing C2, C2 could be discharged to ground before connecting it to V+, which would be easier to implement. Reversing C2 has some advantages though: 1) ΔV2 can be doubled without increasing power dissipation; and 2) the time allowed for settling is doubled (C2 needs to settle only once instead of twice every period). By reversing C2, both a near optimal and a practical choice would be ΔV1 = ΔV2 = 2VDD/3. In the case of a sawtooth waveform, the total core current, Icore, is at least 2I1 in steady state (= I1 + Ī2); the discharge current has to be equal to the charge current. This implies a theoretical FoM of -163.2dBc/Hz at 290K, which is similar to that of ring oscillators. Fig. 2. Block-level schematic of a switched-capacitor relaxation oscillator.  C. Waveform The waveform of the switched-capacitor relaxation oscillator can be a sawtooth waveform, a triangle waveform or anything in between. A sawtooth waveform arises when 176 3current source I2 sources the full discharge packet instantly, i.e. when I2 = C2 ΔV2 / tact = I1 tosc / tact and tact → 0. A triangle waveform arises when I2 = I1 and tact = tosc / 2, i.e. both are a function of frequency. Furthermore, in case of a triangle waveform C1 is halved in size with respect to C1 in case of a sawtooth waveform. IV. TRANSISTOR IMPLEMENTATION AND SIMULATIONS Figure 4 shows the actual implementation of the switched-capacitor relaxation oscillator. I1 is implemented by a resistively degenerated PMOST to increase control linearity and decrease thermal noise. M2 could be biased continuously by I2, but this would worsen the FoM dramatically. Only when C2 is reversed, S2 is closed briefly (during tosc·I1/I2) and I2 discharges C1 through C2 during this time. When S2 is opened, C2 starts settling to Vref,OTA. Note that the accuracy of the charge packet with which C1 is discharged is only a function of the settling of C2; noise on I2 does not affect the accuracy. Vref,OTA is implemented as the gate-source voltage of M2 biased at current I1. The relaxation oscillator of Fig. 4 has been designed in a standard 65nm CMOS process (VDD = 1.2V). The main design choices are: Vref,OTA = VDD/3, Vref,osc = VDD/6, ΔV1 = ΔV2 = ΔV3 = 2VDD/3, I1 = Ī2 = I2/4 = 25μA, C1 = C2 = 2.5pF. The measurement buffers, oscillator comparator and its reference are designed to consume about 2.5mA, 10μA and 5μA, respectively. The circuitry to switch I2 and reverse C2 reliably consumes about 5μA. As a result, fosc = 12.5MHz, Icore = 2.8I1 = 70μA.  According to (2), the FoM is expected to be   Fig. 4. Actual implementation of a switched-capacitor relaxation oscillator.    Fig. 6. Measured phase noise (Agilent E4440A spectrum analyzer, Keithley 2000 multimeter). -161.7dBc/Hz at 290K, which is similar to the -161.4dBc/Hz predicted by simulation. Simulation also predicts a lower oscillation frequency and lower peak voltages than calculated, mainly due to the gate-source and gate-drain capacitances of M2. V. IC IMPLEMENTATION AND MEASUREMENTS The active area of the 65nm CMOS design measures 200x150μm2 [5]. Fig. 5 and 6 show the measurement results. The circuit is measured using a battery supply. It is fully functional and the performance is similar for supply voltages between 1.0 and 1.3V. Unfortunately, S2 is closed for somewhat less than tosc·I1/I2, so the waveform is slightly deformed; this can be easily corrected in a re-design. The measured FoM is Fig. 5. Measured waveforms, frequency tuning range and frequency tuning gain (Agilent DSO6104A oscilloscope and LeCroy AP033 active differential probe, R&S FSP spectrum analyzer). -161dBc/Hz, which is similar to both analysis and simulation results. Ten samples have been measured and all have similar FoMs. VI. CONCLUSION Measurements illustrate the advantages of a relaxation oscillator: the phase can be read out continuously and the tuning range is both large and linear. Measurements also show an outstanding phase noise performance; the FoM is at least 6dB better than state-of-the-art relaxation oscillators [1], [2], 177 4[4] and similar to state-of-the-art ring oscillators [2]. Note that we include all the core current consumption. As it seems to be increasingly more difficult to reach the minimal FoM for ring oscillators in smaller CMOS technologies [2], relaxation oscillators could well become the preferred choice of RC oscillators in low-power applications, like sensor networks. ACKNOWLEDGMENT The authors thank D. Leenaerts and C. Vaucher of NXP Semiconductors for chip fabrication and other valuable resources. REFERENCES   [1] S. L. J. Gierkink, A. J. M. van Tuijl, “A Coupled Sawtooth Oscillator Combining Low Jitter with High Control Linearity,” IEEE J. Solid-State Circuits, pp. 702-710, June 2002. [2] R. Navid, T. H. Lee, R. W. Dutton, “Minimum Achievable Phase Noise of RC Oscillators,” IEEE J. Solid-State Circuits, pp. 630-637, March 2005. [3] M. J. Underhill, “The Adiabatic Anti-Jitter Circuit,” IEEE T. Ultrasonic, Ferroelectrics, and Frequency Control, vol. 48, no. 3, pp. 666–674, May 2001. [4] L. B. Oliveira, et al., “Experimental Evaluation of Phase-Noise and Quadrature Error in a CMOS 2.4 GHz Relaxation Oscillator,” ISCAS, pp. 1461-1464, 2007. [5] P. F. J. Geraedts, A. J. M. van Tuijl, E. A. M. Klumperink, et al., “A 90μW 12MHz Relaxation Oscillator with a -162dB FOM,” ISSCC, Feb. 2008, pp. 348-349. 178

A Coupled Sawtooth Oscillator Combining Low Jitter with High Control Linearity,”

Minimum Achievable Phase

The Adiabatic Anti-Jitter Circuit,”

A 12MHz Switched-Capacitor Relaxation Oscillator with a Nearly Minimal FoM of -161dBc/Hz

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