Design of a Low Offset, Low Noise Amplifier for Neural Recording Applications

The design of a capacitive feedback based neural recording amplifier is presented. The prime design requirements in case of neural amplifiers includes low noise, high gain, high CMRR, low power, low area and low offset voltage. However, there is an inherent trade-off between noise-power and area-offset in the design process which needs to be addressed. A Recycling Folded Cascode based Operational Transconductance Amplifier (RFC-OTA) topology is employed to realize the amplifier as it offers better gain and offset voltage as compared to other topologies. The sizing of the transistors has been done with the primary objective of low random offset voltage while meeting other design criteria within the specified range subject to all inherent trade-offs. Simulations have been done in Cadence Virtuoso using SCL 180 nm technology and comparative analysis with other reported designs reveals that the proposed RFC-OTA based neural amplifier design achieves a low random offset voltage of 1.4 mV with a low input noise of 1.38 µV as compared to most of the reported design

Design of a Low Offset, Low Noise Amplifier for Neural Recording Applications

418-423The design of a capacitive feedback based neural recording amplifier is presented. The prime design requirements in case of neural amplifiers includes low noise, high gain, high CMRR, low power, low area and low offset voltage. However, there is an inherent trade-off between noise-power and area-offset in the design process which needs to be addressed. A Recycling Folded Cascode based Operational Transconductance Amplifier (RFC-OTA) topology is employed to realize the amplifier as it offers better gain and offset voltage as compared to other topologies. The sizing of the transistors has been done with the primary objective of low random offset voltage while meeting other design criteria within the specified range subject to all inherent trade-offs. Simulations have been done in Cadence Virtuoso using SCL 180 nm technology and comparative analysis with other reported designs reveals that the proposed RFC-OTA based neural amplifier design achieves a low random offset voltage of 1.4 mV with a low input noise of 1.38 µV as compared to most of the reported design

Optimized Design of a Self-Biased Amplifier for Seizure Detection Supplied by Piezoelectric Nanogenerator: Metaheuristic Algorithms versus ANN-Assisted Goal Attainment Method

This work is dedicated to parameter optimization for a self-biased amplifier to be used in preamplifiers for the diagnosis of seizures in neuro-diseases such as epilepsy. For the sake of maximum compactness, which is obligatory for all implantable devices, power is to be supplied by a piezoelectric nanogenerator (PENG). Several meta-heuristic optimization algorithms and an ANN (artificial neural network)-assisted goal attainment method were applied to the circuit, aiming to provide us with the set of optimal design parameters which ensure the minimal overall area of the preamplifier. These parameters are the slew rate, load capacitor, gain–bandwidth product, maximal input voltage, minimal input voltage, input voltage, reference voltage, and dissipation power. The results are re-evaluated and compared in the Cadence 180 nm SCL environment. It has been observed that, among the metaheuristic algorithms, the whale optimization technique reached the best values at low computational cost, decreased complexity, and the highest convergence speed. However, all metaheuristic algorithms were outperformed by the ANN-assisted goal attainment method, which produced a roughly 50% smaller overall area of the preamplifier. All the techniques described here are applicable to the design and optimization of wearable or implantable circuits

A Low Noise Amplifier for Neural Spike Recording Interfaces

This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 Vrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz–7.4 kHz and consumes 1.92 W. The performance of the proposed LNA has been validated through in vivo experiments with animal modelsWe acknowledge support by the CSIC Open Access Publication Initiative through its Unit of Information Resources for Research (URICI)Peer reviewe