A Faithful Semantics for Generalised Symbolic Trajectory Evaluation

Generalised Symbolic Trajectory Evaluation (GSTE) is a high-capacity formal verification technique for hardware. GSTE uses abstraction, meaning that details of the circuit behaviour are removed from the circuit model. A semantics for GSTE can be used to predict and understand why certain circuit properties can or cannot be proven by GSTE. Several semantics have been described for GSTE. These semantics, however, are not faithful to the proving power of GSTE-algorithms, that is, the GSTE-algorithms are incomplete with respect to the semantics. The abstraction used in GSTE makes it hard to understand why a specific property can, or cannot, be proven by GSTE. The semantics mentioned above cannot help the user in doing so. The contribution of this paper is a faithful semantics for GSTE. That is, we give a simple formal theory that deems a property to be true if-and-only-if the property can be proven by a GSTE-model checker. We prove that the GSTE algorithm is sound and complete with respect to this semantics

GSTE is partitioned model checking

Verifying whether an ω-regular property is satisfied by a finite-state system is a core problem in model checking. Standard techniques build an automaton with the complementary language, compute its product with the system, and then check for emptiness. Generalized symbolic trajectory evaluation (GSTE) has been recently proposed as an alternative approach, extending the computationally efficient symbolic trajectory evaluation (STE) to general ω-regular properties. In this paper, we show that the GSTE algorithms are essentially a partitioned version of standard symbolic model-checking (SMC) algorithms, where the partitioning is driven by the property under verification. We export this technique of property-driven partitioning to SMC and show that it typically does speed up SMC algorithm

Intelligent Modeling and Verification (Editorial)

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A Hybrid Hardware Verification Technique in FPGA Design

Assertion-based verification (ABV) is best emerging technique for verification of industrial hardware. Property Specification Language (PSL) is one of the most important components of ABV. In this paper we present a method to emulate hardware that is capable of support ABV that in it assertion expressions mapped to HDL. We simulated this method by an applicable example by Modelsim software. Test results indicate that this method performance is good

A Hybrid Hardware Verification Technique in FPGA Design

Assertion-based verification (ABV) is best emerging technique for verification of industrial hardware. Property Specification Language (PSL) is one of the most important components of ABV. In this paper we present a method to emulate hardware that is capable of support ABV that in it assertion expressions mapped to HDL. We simulated this method by an applicable example by Modelsim software. Test results indicate that this method performance is good