Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

Recent advances in the hardware architecture of flat display devices

Thesis (Master)--Izmir Institute of Technology, Electronics and Communication Engineering, Izmir, 2007Includes bibliographical References (leaves: 115-117)Text in English; Abstract: Turkish and Englishxiii, 133 leavesThesis will describe processing board hardware design for flat panel displays with integrated digital reception, the design challenges in flat panel displays with integrated digital reception explained with details. Thesis also includes brief explanation of flat panel technology and processing blocks. Explanations of building blocks of TV and flat panel displays are given before design stage for better understanding of design stage. Hardware design stage of processing board is investigated in two major steps, schematic design and layout design. First step of the schematic design is system level block diagram design. Schematic diagram is the detailed application level hardware design and layout is the implementation level of the design. System level, application level and implementation level hardware design of the TV processing board is described with details in thesis. Design challenges, considerations and solutions are defined in advance for flat panel displays

CMOS RF front-end design for terrestrial and mobile digital television systems

With the increasing demand for high quality TV service, digital television (DTV) is replacing the conventional analog television. DTV tuner is one of the most critical blocks of the DTV receiver system; it down-converts the desired DTV RF channel to baseband or a low intermediate frequency with enough quality. This research is mainly focused on the analysis and realization of low-cost low-power front-ends for ATSC terrestrial DTV and DVB-H mobile DTV tuner systems. For the design of the ATSC terrestrial tuner, a novel double quadrature tuner architecture, which can not only minimize the tuner power consumption but also achieve the fully integration, has been proposed. A double quadrature down-converter has been designed and fabricated with TSMC 0.35õm CMOS technology; the measurement results verified the proposed concepts. For the mobile DTV tuner, a zero-IF architecture is used and it can achieve the DVB-H specifications with less than 200mW power consumption. In the implementation of the mobile DVB-H tuner, a novel RF variable gain amplifier (RFVGA) and a low flicker noise current-mode passive mixer have been proposed. The proposed RFVGA achieves high dynamic range and robust input impedance matching performance, which is the main design challenge for the traditional implementations. The current-mode passive mixer achieves high-gain, low noise (especially low flicker noise) and high-linearity (over 10dBm IIP3) with low power supplies; it is believed that this is a promising topology for low voltage high dynamic range mixer applications. The RFVGA has been fabricated in TSMC 0.18õm CMOS technology and the measurement results agree well with the theoretical ones

BiCMOS high-performance ICs : from DC to mm-wave

Progress with silicon and silicon germanium (SiGe) based BiCMOS technologies over the past few years has been very impressive. This enables the implementation of traditional microwave and emerging mm-wave applications in silicon. The paper gives an overview of several high-performance ICs that have been implemented in a state-of-the-art BiCMOS technology (QUBiC4). Examples of high-performance ICs are described ranging from basic building blocks for mobile applications to highly integrated receiver and transmitter ICs for applications up to the mm-wave range

A Digital Sine-Weighted switched-Gm mixer for Single-Clock Power-Scalable parallel receivers

Abstract— This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NFand better than 75 dB inter-receiver isolation

Television broadcast from space systems: Technology, costs

Broadcast satellite systems are described. The technologies which are unique to both high power broadcast satellites and small TV receive-only earth terminals are also described. A cost assessment of both space and earth segments is included and appendices present both a computer model for satellite cost and the pertinent reported experience with the Japanese BSE