Hardware Impairments Aware Transceiver Design for Bidirectional Full-Duplex MIMO OFDM Systems

In this paper we address the linear precoding and decoding design problem for a bidirectional orthogonal frequencydivision multiplexing (OFDM) communication system, between two multiple-input multiple-output (MIMO) full-duplex (FD) nodes. The effects of hardware distortion as well as the channel state information error are taken into account. In the first step, we transform the available time-domain characterization of the hardware distortions for FD MIMO transceivers to the frequency domain, via a linear Fourier transformation. As a result, the explicit impact of hardware inaccuracies on the residual selfinterference (RSI) and inter-carrier leakage (ICL) is formulated in relation to the intended transmit/received signals. Afterwards, linear precoding and decoding designs are proposed to enhance the system performance following the minimum-mean-squarederror (MMSE) and sum rate maximization strategies, assuming the availability of perfect or erroneous CSI. The proposed designs are based on the application of alternating optimization over the system parameters, leading to a necessary convergence. Numerical results indicate that the application of a distortionaware design is essential for a system with a high hardware distortion, or for a system with a low thermal noise variance.Comment: Submitted to IEEE for publicatio

Hybrid Beam-Steering OFDM-MIMO Radar: High 3-D Resolution With Reduced Channel Count

We report on the realization of a multichannel imaging radar that achieves uniform 2-D cross-range resolution by means of a linear array of a special form of leaky-wave antennas. The presented aperture concept enables a tradeoff between the available range resolution and a reduction in the number of channels required for a given angular resolution. The antenna front end is integrated within a multichannel radar based on stepped-carrier orthogonal frequency-division modulation, and the advantages and challenges specific to this combination are analyzed with respect to signal processing and a newly developed calibration routine. The system concept is fully implemented and verified in the form of a mobile demonstrator capable of soft real-time 3-D processing. By combining radio frequency (RF) components operating in the W-band (85-105 GHz) with the presented aperture, a 3-D resolution of less than 1.5° x 1.5° x 15 cm is demonstrated using only eight transmitters and eight receivers

Experimental Evaluation of Hybrid Fibre−Wireless System for 5G Networks

This article describes a novel experimental study considering a multiband fibre–wireless system for constructing the transport network for fifth-generation (5G) networks. This study describes the development and testing of a 5G new radio (NR) multi-input multi-output (MIMO) hybrid fibre–wireless (FiWi) system for enhanced mobile broadband (eMBB) using digital pre-distortion (DPD). Analog radio over fibre (A-RoF) technology was used to create the optical fronthaul (OFH) that includes a 3 GHz supercell in a long-range scenario as well as a femtocell scenario using the 20 GHz band. As a proof of concept, a Mach Zehnder modulator with two independent radio frequency waveforms modifies a 1310 nm optical carrier using a distributed feedback laser across 10 km of conventional standard single-mode fibre. It may be inferred that a hybrid FiWi-based MIMO-enabled 5G NR system based on OFH could be a strong competitor for future mobile haul applications. Moreover, a convolutional neural network (CNN)-based DPD is used to improve the performance of the link. The error vector magnitude (EVM) performance for 5G NR bands is predicted to fulfil the Third Generation Partnership Project’s (3GPP) Release 17 standards

Smart antennas: state of the art

Aim of this contribution is to illustrate the state of the art of smart antenna research from several perspectives. The bow is drawn from transmitter issues via channel measurements and modeling, receiver signal processing, network aspects, technological challenges towards first smart antenna applications and current status of standardization. Moreover, some future prospects of different disciplines in smart antenna research are given.Peer Reviewe

Radio frequency-chain selection for energy and spectral efficiency maximization in hybrid beamforming under hardware imperfections

The next-generation wireless communications require reduced energy consumption, increased data rates and better signal coverage. The millimetre-wave frequency spectrum above 30 GHz can help fulfil the performance requirements of the next-generation mobile broadband systems. Multiple-input multiple-output technology can provide performance gains to help mitigate the increased path loss experienced at millimetre-wave frequencies compared with microwave bands. Emerging hybrid beamforming architectures can reduce the energy consumption and hardware complexity with the use of fewer radio-frequency (RF) chains. Energy efficiency is identified as a key fifth-generation metric and will have a major impact on the hybrid beamforming system design. In terms of transceiver power consumption, deactivating parts of the beamformer structure to reduce power typically leads to significant loss of spectral efficiency. Our aim is to achieve the highest energy efficiency for the millimetre-wave communications system while mitigating the resulting loss in spectral efficiency. To achieve this, we propose an optimal selection framework which activates specific RF chains that amplify the digitally beamformed signals with the analogue beamforming network. Practical precoding is considered by including the effects of user interference, noise and hardware impairments in the system modelling

Radio-frequency chain selection for energy and spectral efficiency maximization in hybrid beamforming under hardware imperfections

The next-generation wireless communications require reduced energy consumption, increased data rates and better signal coverage. The millimetre-wave frequency spectrum above 30 GHz can help fulfil the performance requirements of the next-generation mobile broadband systems. Multiple-input multiple-output technology can provide performance gains to help mitigate the increased path loss experienced at millimetre-wave frequencies compared with microwave bands. Emerging hybrid beamforming architectures can reduce the energy consumption and hardware complexity with the use of fewer radio-frequency (RF) chains. Energy efficiency is identified as a key fifth-generation metric and will have a major impact on the hybrid beamforming system design. In terms of transceiver power consumption, deactivating parts of the beamformer structure to reduce power typically leads to significant loss of spectral efficiency. Our aim is to achieve the highest energy efficiency for the millimetre-wave communications system while mitigating the resulting loss in spectral efficiency. To achieve this, we propose an optimal selection framework which activates specific RF chains that amplify the digitally beamformed signals with the analogue beamforming network. Practical precoding is considered by including the effects of user interference, noise and hardware impairments in the system modelling

SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios

Modern design of Software-Defined Radio (SDR) applications is based on Field Programmable Gate Arrays (FPGA) due to their ability to be configured into solution architectures that are well suited to domain-specific problems while achieving the best trade-off between performance, power, area, and flexibility. FPGAs are well known for rich computational resources, which traditionally include logic, register, and routing resources. The increased technological advances have seen FPGAs incorporating more complex components that comprise sophisticated memory blocks, Digital Signal Processing (DSP) blocks, and high-speed interfacing to Gigabit Ethernet (GbE) and Peripheral Component Interconnect Express (PCIe) bus. Gateware for programming FPGAs is described at a lowlevel of design abstraction using Register Transfer Language (RTL), typically using either VHSIC-HDL (VHDL) or Verilog code. In practice, the low-level description languages have a very steep learning curve, provide low productivity for hardware designers and lack readily available open-source library support for fundamental designs, and consequently limit the design to only hardware experts. These limitations have led to the adoption of High-Level Synthesis (HLS) tools that raise design abstraction using syntax, semantics, and software development notations that are well-known to most software developers. However, while HLS has made programming of FPGAs more accessible and can increase the productivity of design, they are still not widely adopted in the design community due to the low-level skills that are still required to produce efficient designs. Additionally, the resultant RTL code from HLS tools is often difficult to decipher, modify and optimize due to the functionality and micro-architecture that are coupled together in a single High-Level Language (HLL). In order to alleviate these problems, Domain-Specific Languages (DSL) have been introduced to capture algorithms at a high level of abstraction with more expressive power and providing domain-specific optimizations that factor in new transformations and the trade-off between resource utilization and system performance. The problem of existing DSLs is that they are designed around imperative languages with an instruction sequence that does not match the hardware structure and intrinsics, leading to hardware designs with system properties that are unconformable to the high-level specifications and constraints. The aim of this thesis is, therefore, to design and implement an intermediatelevel framework namely SdrLift for use in high-level rapid prototyping of SDR applications that are based on an FPGA. The SdrLift input is a HLL developed using functional language constructs and design patterns that specify the structural behavior of the application design. The functionality of the SdrLift language is two-fold, first, it can be used directly by a designer to develop the SDR applications, secondly, it can be used as the Intermediate Representation (IR) step that is generated by a higher-level language or a DSL. The SdrLift compiler uses the dataflow graph as an IR to structurally represent the accelerator micro-architecture in which the components correspond to the fine-level and coarse-level Hardware blocks (HW Block) which are either auto-synthesized or integrated from existing reusable Intellectual Property (IP) core libraries. Another IR is in the form of a dataflow model and it is used for composition and global interconnection of the HW Blocks while making efficient interfacing decisions in an attempt to satisfy speed and resource usage objectives. Moreover, the dataflow model provides rules and properties that will be used to provide a theoretical framework that formally analyzes the characteristics of SDR applications (i.e. the throughput, sample rate, latency, and buffer size among other factors). Using both the directed graph flow (DFG) and the dataflow model in the SdrLift compiler provides two benefits: an abstraction of the microarchitecture from the high-level algorithm specifications and also decoupling of the microarchitecture from the low-level RTL implementation. Following the IR creation and model analyses is the VHDL code generation which employs the low-level optimizations that ensure optimal hardware design results. The code generation process per forms analysis to ensure the resultant hardware system conforms to the high-level design specifications and constraints. SdrLift is evaluated by developing representative SDR case studies, in which the VHDL code for eight different SDR applications is generated. The experimental results show that SdrLift achieves the desired performance and flexibility, while also conserving the hardware resources utilized