90 research outputs found
Stall Pattern Avoidance in Polynomial Product Codes
Product codes are a concatenated error-correction scheme that has been often
considered for applications requiring very low bit-error rates, which demand
that the error floor be decreased as much as possible. In this work, we
consider product codes constructed from polynomial algebraic codes, and propose
a novel low-complexity post-processing technique that is able to improve the
error-correction performance by orders of magnitude. We provide lower bounds
for the error rate achievable under post processing, and present simulation
results indicating that these bounds are tight.Comment: 4 pages, 2 figures, GlobalSiP 201
Nouvelles stratégies de concaténation de codes séries pour la réduction du seuil d’erreur dans le contrôle de parité à faible densité et dans les turbo codes produits
This paper presents a novel multiple serial code concatenation (SCC) strategy to combat the error-floor problem in iterated sparse graph-based error correcting codes such as turbo product-codes (TPC) and low-density parity-check (LDPC) codes. Although SCC has been widely used in the past to reduce the error-floor in iterative decoders, the main stumbling block for its practical application in high-speed communication systems has been the need for long and complex outer codes. Alternative, short outer block codes with interleaving have been shown to provide a good tradeoff between complexity and performance. Nevertheless, their application to next-generation high-speed communication systems is still a major challenge as a result of the careful design of long complex interleavers needed to meet the requirements of these applications. The SCC scheme proposed in this work is based on the use of short outer block codes. Departing from techniques used in previous proposals, the long outer code and interleaver are replaced by a simple block code combined with a novel encoding/decoding strategy. This allows the proposed SCC to provide a better tradeoff between performance and complexity than previous techniques. Several application examples showing the benefits of the proposed SCC are described. Particularly, a new coding scheme suitable for high-speed optical communication is introduced.Fil: Morero, Damián Alfonso. Universidad Nacional de Cordoba. Facultad de Ciencias Exactas, Fisicas y Naturales; ArgentinaFil: Hueda, Mario Rafael. Universidad Nacional de Cordoba. Facultad de Ciencias Exactas, Fisicas y Naturales; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba; Argentin
Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder
Variable-rate transceivers, which adapt to the conditions, will be central to energy-efficient communication. However, fiber-optic communication systems with high bit-rate requirements make design of flexible transceivers challenging, since additional circuits needed to orchestrate the flexibility will increase area and degrade speed. We propose a variable-rate VLSI architecture of a forward error correction (FEC) decoder based on hard-decision product codes. Variable shortening of component codes provides a mechanism by which code rate can be varied, the number of iterations offers a knob to control the coding gain, while a key-equation solver module that can swap between error-locator polynomial coefficients provides a means to change error correction capability. Our evaluations based on 28-nm netlists show that a variable-rate decoder implementation can offer a net coding gain (NCG) range of 9.96-10.38 dB at a post-FEC bit-error rate of 10^-15. The decoder achieves throughputs in excess of 400 Gb/s, latencies below 53 ns, and energy efficiencies of 1.14 pJ/bit or less. While the area of the variable-rate decoder is 31% larger than a decoder with a fixed rate, the power dissipation is a mere 5% higher. The variable error correction capability feature increases the NCG range further, to above 10.5 dB, but at a significant area cost
Staircase Codes: FEC for 100 Gb/s OTN
Staircase codes, a new class of forward-error-correction (FEC) codes suitable
for high-speed optical communications, are introduced. An ITU-T
G.709-compatible staircase code with rate R=239/255 is proposed, and FPGA-based
simulation results are presented, exhibiting a net coding gain (NCG) of 9.41 dB
at an output error rate of 1E-15, an improvement of 0.42 dB relative to the
best code from the ITU-T G.975.1 recommendation. An error floor analysis
technique is presented, and the proposed code is shown to have an error floor
at 4.0E-21.Comment: To appear in IEEE/OSA J. of Lightwave Technolog
Codificación para corrección de errores con aplicación en sistemas de transmisión y almacenamiento de información
Tesis (DCI)--FCEFN-UNC, 2013Trata de una técnica de diseño de códigos de chequeo de paridad de baja densidad ( más conocidas por sigla en ingles como LDPC) y un nuevo algoritmo de post- procesamiento para la reducción del piso de erro
Binary Message Passing Decoding of Product-like Codes
We propose a novel binary message passing decoding algorithm for product-like
codes based on bounded distance decoding (BDD) of the component codes. The
algorithm, dubbed iterative BDD with scaled reliability (iBDD-SR), exploits the
channel reliabilities and is therefore soft in nature. However, the messages
exchanged by the component decoders are binary (hard) messages, which
significantly reduces the decoder data flow. The exchanged binary messages are
obtained by combining the channel reliability with the BDD decoder output
reliabilities, properly conveyed by a scaling factor applied to the BDD
decisions. We perform a density evolution analysis for generalized low-density
parity-check (GLDPC) code ensembles and spatially coupled GLDPC code ensembles,
from which the scaling factors of the iBDD-SR for product and staircase codes,
respectively, can be obtained. For the white additive Gaussian noise channel,
we show performance gains up to dB and dB for product and
staircase codes compared to conventional iterative BDD (iBDD) with the same
decoder data flow. Furthermore, we show that iBDD-SR approaches the performance
of ideal iBDD that prevents miscorrections.Comment: Accepted for publication in the IEEE Transactions on Communication
Design tradeoffs and challenges in practical coherent optical transceiver implementations
This tutorial discusses the design and ASIC implementation of coherent optical transceivers. Algorithmic and architectural options and tradeoffs between performance and complexity/power dissipation are presented. Particular emphasis is placed on flexible (or reconfigurable) transceivers because of their importance as building blocks of software-defined optical networks. The paper elaborates on some advanced digital signal processing (DSP) techniques such as iterative decoding, which are likely to be applied in future coherent transceivers based on higher order modulations. Complexity and performance of critical DSP blocks such as the forward error correction decoder and the frequency-domain bulk chromatic dispersion equalizer are analyzed in detail. Other important ASIC implementation aspects including physical design, signal and power integrity, and design for testability, are also discussed.Fil: Morero, Damián Alfonso. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; Argentina. ClariPhy Argentina S.A.; ArgentinaFil: Castrillon, Alejandro. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; ArgentinaFil: Aguirre, Alejandro. ClariPhy Argentina S.A.; ArgentinaFil: Hueda, Mario Rafael. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados en Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Instituto de Estudios Avanzados en Ingeniería y Tecnología; ArgentinaFil: Agazzi, Oscar Ernesto. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; Argentina. ClariPhy Argentina S.A.; Argentin
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