Implementation of LS, MMSE and SAGE Channel Estimators for Mobile MIMO-OFDM

The use of decision directed (DD) channel estimation in a multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) downlink receiver is studied in this paper. The 3GPP long term evolution (LTE) based pilot structure is used as a benchmark. The space-alternating generalized expectation-maximization (SAGE) algorithm is used to improve the performance from that of the pilot symbol based least-squares (LS) channel estimator. The DD channel estimation improves the performance with high user velocities, where the pilot symbol density is not sufficient. Minimum mean square error (MMSE) filtering can also be used in estimating the channel in between pilot symbols. The DD channel estimation can be used to reduce the pilot overhead without any performance degradation by transmitting data instead of pilot symbols. The pilot overhead is reduced to a third of the LTE pilot overhead, obtaining a ten percent increase in throughput. The pilot based LS, MMSE and the SAGE channel estimators are implemented and the performance-complexity trade-offs are studied

Decision-Directed Channel Estimation Implementation for Spectral Efficiency Improvement in Mobile MIMO-OFDM

Channel estimation algorithms and their implementations for mobile receivers are considered in this paper. The 3GPP long term evolution (LTE) based pilot structure is used as a benchmark in a multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) receiver. The decision directed (DD) space alternating generalized expectation-maximization (SAGE) algorithm is used to improve the performance from that of the pilot symbol based least-squares (LS) channel estimator. The performance is improved with high user velocities, where the pilot symbol density is not sufficient. Minimum mean square error (MMSE) filtering is also used in estimating the channel in between pilot symbols. The pilot overhead can be reduced to a third of the LTE pilot overhead with DD channel estimation, obtaining a ten percent increase in data throughput. Complexity reduction and latency issues are considered in the architecture design. The pilot based LS, MMSE and the SAGE channel estimators are implemented with a high level synthesis tool, synthesized with the UMC 0.18 μm CMOS technology and the performance-complexity trade-offs are studied. The MMSE estimator improves the performance from the simple LS estimator with LTE pilot structure and has low power consumption. The SAGE estimator has high power consumption but can be used with reduced pilot density to increase the data rate.National Science FoundationTekesElektrobitRenesas Mobile EuropeAcademy of FinlandNokia Siemens NetworksXilin

A high performance VLSI FFT architecture

High performance VLSI-based FFT architectures are key to signal processing and telecommunication systems since they meet the hard real-time constraints at low silicon area and low power compared to CPU-based solutions. In order to meet these goals, this paper presents a novel VLSI FFT architecture based on combining three consecutive radix-4 stages to result in a 64-point FFT engine. Cascading these 64-point FFT engines consequences an improved architecture design featuring certain characteristics. First, it can efficiently accommodate large input data sets in real time. It also simplifies processing requirements due to the radix-4 calculations. Finally, it reduces memory requirements and latency to one third compared to the fully unfolded radix-4 architecture. Two different implementations are utilized in order to validate the architecture efficiency: a FPGA implementation of a 4096-point FFT achieving a throughput of 4096 point/20.48 usec, and a VLSI implementation sustaining a throughput of 4096 point/3.89 usec